lan83c175 Standard Microsystems Corp., lan83c175 Datasheet - Page 44

• Manufacturer Part Number: lan83c175
• Description: Ethernet Cardbus Integrated Controller With Modem Support Corporation
• Manufacturer: Standard Microsystems Corp.

2C - RECEIVE FIFO
Reset Value: xxxxxxxxxxxxxxxx
31 through 16 - Unused.
15 through 0 - The receive fifo can be read
and written through this I/O port (for test
purposes only). The upper and lower 16 bits
of each word in the receive fifo are muxed into
this space.
30
CONTROL
Reset Value: 00000000000000
This register provides management interface
control for functions such as read, write, and
synchronize. It also contains the PHY address
field and the PHY register address field to be
sent in the command word to the PHY.
management operation is executed by a
writing the corresponding operation bit to this
register. When the operation is complete, the
bit will be automatically cleared.
31 through 14: Unused.
13 through 9 - PHY ADDRESS FIELD: This 5
bit field is sent in the management frame to
the PHY. D13 is the MSB.
8 through 4 - PHY REGISTER ADDRESS
FIELD: This 5 bit field is sent in the
management frame to the PHY. D8 is the
MSB.
3 - RESPONDER: This bit returns a 1 during
a read operation if a PHY responded with a
zero level on the MDIO line during the first
SMCLK cycle following the idle bit time when
both the management entity and the PHY do
not drive the MDIO. This bit can be used to
-
MII
MANAGEMENT
INTERFACE
A
44
determine if a PHY responded to the read
operation.
register read. This bit is read only.
2 - Unused.
1 - WRITE: This bit is set to 1 to initiate a write
operation on the management interface. When
set, a properly formatted management frame is
sent to the PHY.
management frame is filled with the contents of
the Management Interface Data register. The bit
is self clearing after completion of the operation.
0 - READ: This bit is set to 1 to initiate a read
operation on the management interface. When
set, a properly formatted management frame will
be sent on the MDIO line with corresponding
cycles on MDC. Data returned by the PHY is
shifted into the Management
register. The bit is self clearing after completion
of the operation.
34 - MII MANAGEMENT INTERFACE DATA
Reset Value: 0000000000000000
This 16 bit register is used by the MII
management unit for all data transfers between
the management and PHY(s).
31 through 16: Unused.
15 through 0 -
written to this register will be used in the data field
of a management interface write operation. For
read operations, this 16-bit value will store the
data transferred from the PHY.
38 - MII CONFIGURATION
Reset Value: 0001XX00
This register provides MII configuration functions.
31 through 8: Unused.
This bit is self clearing following a
FRAME DATA: A 16 bit value
The data field of the
Interface Data