lan83c175 Standard Microsystems Corp., lan83c175 Datasheet - Page 30

• Manufacturer Part Number: lan83c175
• Description: Ethernet Cardbus Integrated Controller With Modem Support Corporation
• Manufacturer: Standard Microsystems Corp.

The data transfer process can be inhibited by
operating in monitor mode. This mode checks
validiity of incoming frames and maintains error
statistics, but does not store the frame in
memory. Frames which would otherwise have
been accepted cause the Missed Packet counter
to increment upon completion of the frame.
If the receive local memory becomes full during
reception of a frame, the frame is aborted. The
host is notified of the condition with an overflow
interrupt.
counter is incremented for each frame which
could not be received due to the overflow
condition.
Error Checking
Received frames are checked for CRC and
alignment errors.
frame is incorrect, a CRC error is indicated in
the status register and the CRC error counter is
incremented. Reception of the frame is aborted
unless the receiver has been programmed to
receive errored packets. If the frame does not
terminate on a byte boundary and the CRC is
incorrect, then an alignment error is also
indicated in the status register.
occurs, the alignment error counter will be
incremented.
generated when a CRC error is detected and
monitor mode is not set.
The receive control register can be programmed
to enable long frame checking (frames longer
than 1518 bytes).
detected the CRC and alignment counters are
not incremented.
Status
A status register is updated at the completion of
each frame whether it completed normally or
aborted in error.
important information about the frame until it is
transferred with the packet data to the receive
local memory. If the frame data is not being
Additionally, the missed
A receive error interrupt is
If the CRC of a received
The status register holds
When a long frame is
When this
packet
30
saved due to an error or monitor mode, then the
contents of the status register will be lost after
the completion of the following packet.
description of the status register contents is
located in the register definition section of this
data sheet.
Event Counters
Three event counters record CRC errors,
alignment errors, and missed packets.
counters are all 8-bits wide and count from zero
to 255. At 255 the counters stop until they have
been read by the host. The counters are self
clearing after the read. The counters generate a
shared interrupt when any one of them reaches
a count of 192.
The counter is also incremented for receive local
memory full errors. The missed packet counter
is 8 bits wide and generates an interrupt when
MAC TRANSMITTER
The
capable of generating network data at rates of
10 and 100 Mbps.
implementations of 10 Mbps physical layer
devices, and the 802.3u Media Independent
Interface (MII) for 10 and 100 Mbps.
Basic Function
The transmitter
wide data streams at 10 or 100 Mbps. It forms
a proper preamble and SFD field at the
beginning of each packet. The frame data is
then shifted serially or by nibbles from an
internal transmit buffer to the physical layer. The
transmitter completes the packet by computing
and appending the CRC field.
transmission, the transmitter monitors the
network for collisions and retransmits frames
after
necessary.
transmit
it reaches a count of 192.
LAN83C175
the
statistics
a
The transmitter maintains the
random
generates serial and nibble
CSMA/CD
and
backoff
It supports current
generates
transmitter
During packet
time
status
when
The
is
A