s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 44

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

S1R72900F00A
Having input the final bit of the packet data, the Link layer controller IC inputs Idle ('00b') or Hold ('01b') for one SCLK
cycle and Idle for another SCLK cycle. Then the SIR72900F00A takes over the control of the PHY/LINK interface.
This Hold ('01b') bit ensures that the Link layer controller IC transmits the next packet without giving up the serial bus
(concatenated packet). On detecting a Hold bit, the SIR72900F00A outputs Transmit again to the CTL pin of the Link
layer controller IC after the MIN_PACKET_SEPARATION time. The Link layer controller IC then transmits packets.
The Hold operation is used to transmit a response packet after an Ack packet or to transmit multiple isochronous packets
within the same isochronous cycle (subaction concatenation).
In transmitting a Concatenated packet, the SIR72900F00A determines the Concatenated packet transmission speed
according to the Enab_multi bit of PHY Register 5.
When the Enab_multi bit is set to '0,' the SIR72900F00A recognizes that the transmission speed for the second and later
packets is the same as that for the first packet.
On the other hand, when the Enab_multi bit is set to '1,' the SIR72900F00A recognizes the transmission speed for the
Concatenated packet according to the SP value input to D while Hold ('01b') is being input to CTL.Table 7.12 shows
the meaning of the SP value.
However, the IEEE 1394 standards defines a transmission speed limit for Concatenated packets, prohibiting the
transmission of a Concatenated packet at a speed of S100 after packet transmission at S200 or higher.
To observe the speed limit, when the SIR72900F00A receives a request for 100-Mbps Concatenated packet
transmission following a request for packet transmission at 200 Mbps or higher, it gives up the 1394 bus and performs
arbitration in an attempt to transmit the 100-Mbps packet as a Single packet. Therefore, this 100-Mbps Concatenated
packet transmission request from the Link layer controller IC will be handled as a bus request that occurs in ordinary
LREQ, which may cause the IC to return CTL other than Grant (the request may be canceled).
Packet transmission can be cancelled in the following two ways.
After the Link layer controller IC takes control of the PHY/LINK interface, input Idle ('00b') for three SCLK cycles to
give up the interface. Or, after the Link layer controller IC inputs Hold ('01b') to hold the bus, input Idle for two SCLK
cycles to give up the interface.
Empty packets are output to the serial bus.
7.4.4.4 Receive
On receiving a packet, the SIR72900F00A outputs Receive ('10b') to the CTL pin, and 'H' to the D pin of the Link layer
controller IC. Then the SIR72900F00A outputs a speed code (SP) to start packet data output. The SIR72900F00A
continues to assert Receive ('10b') to the CTL terminal until the data reception completes. Then the SIR72900F00A
asserts Idle ('00b') to declare that the packet reception has completed.
As Receive operation, the SIR72900F00A outputs to the Link interface the Self-ID packets it transmits during the Self-
ID period.
Also as Receive operation, the SIR72900F00A outputs to the Link interface, the response packets to the Extended PHY
packet sent to the node.
Once asserting Receive, the SIR72900F00A may terminate reception operation without outputting packet data.
If the Link layer controller IC supports a transmission speed of 100 Mbps only, it must confirm the speed code (SP) to
make sure that packet data received at 200 or 400 Mbps is ignored.
If the Link layer controller IC supports transmission speeds of 100 and 200 Mbps only, it must confirm the speed code
(SP) to make sure that packet data received at 400 Mbps is ignored.
EPSON
40
Rev. 1.0