s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 19

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

7.1.3.2 Register 01
Bits 0 to 2: Negotiated speed
Bit 3: Enable port event interrupt
Bit 4: Fault
Bits 5 to 7: Reserved
7.1.3.3 Register 02
Bits 0 to 7: Reserved
Rev. 1.0
These bits indicate the speed of the node connected to the port.
They are initialized by bus reset, and determined during a Self-ID period.
The meaning of these bits is as follows:
When this bit is set to '1,' the Port_event bit is set to '1' when a change in the Connected, Bias, Disabled, or Fault bit
occurs.
This bit is initialized as hardware reset occurs.
When this bit is '1,' it indicates that an error has occurred during suspend/resume operation.
This bit is cleared when hardware reset occurs or '1' is written.
Address
Address
0x0A
0x09
'000b': The maximum transmission speed is 100 Mbps.
'001b': The maximum transmission speed is 200 Mbps.
'010b': The maximum transmission speed is 400 Mbps.
0: Negotiated_speed [0]
1: Negotiated_speed [1]
2: Negotiated_speed [2]
3: Int_enable
4: Fault
5: Reserved
6: Reserved
7: Reserved
0: Reserved
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: Reserved
6: Reserved
7: Reserved
Bit Symbol
Bit Symbol
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Power Reset Value
Power Reset Value
EPSON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Negotiated speed
Negotiated speed
Negotiated speed
Enable port event interrupt
fault
Description
Description
S1R72900F00A
15