s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 41

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

An acceleration control request uses the 6-bit-long format as shown in Table 7.12.
With FairReq and PriReq, the Link layer controller IC must start issuing LREQ after at least 1 SCLK after CTL starts
the Idle operation. When CTL starts the Receive operation during or after the Link layer controller IC's issuance of these
requests, the SIR72900F00A cancels them. Therefore, the Link layer controller IC must issue these requests again next
time CTL starts the Idle operation.
However, when the Enab_accel bit of PHY Register 5 is set to '1,' acceleration arbitration (Ack-Acceleration arbitration
and Fly-by arbitration) is enabled, and an Ack packet (8-bit-long packet) is to be received, these requests are not
canceled if the Receive operation starts.
The cycle master Link layer controller IC issues PriReq to transmit a cycle start packet.
The Link layer controller IC issues IsoReq to transmit an isochronous packet. IsoReq must be issued during or within
eight SCLK cycles of transmission of a cycle start packet or an isochronous packet, or during or within four SCLK cycles
of reception of such packets.
The SIR72900F00A clears IsoReq only when it wins arbitration and transmits Grant to the Link layer controller IC, it
detects a subaction gap, or when a bus request occurs.
To transmit an Ack packet, ImmReq is issued during or within four SCLK cycles of reception of a Link packet. To satisfy
ACK_RESPONSE_TIME, the Link layer controller IC must issue ImmReq immediately as it confirms the destination_ID
of the received packet to check that the packet is sent to the node. As soon as the SIR72900F00A receives the packet,
it acquires a bus, and the Link layer controller IC returns Grant. If the Link layer controller IC detects a CRC error, it
must cancel the request rather than send data in response to the Grant. (See 7.4.4.3 Transmit.)
Rev. 1.0
LREQ[1:3]
8 to 15
Bit(s)
Bit(s)
1 to 3
4 to 7
1 to 3
000
001
010
011
100
101
110
111
16
0
0
4
5
Request Type
Request Type
Accelerate
Reserved
ImmReq
Address
Start Bit
Start Bit
FairReq
Stop Bit
IsoReq
AccCtrl
PriReq
RdReg
WrReg
Data
Typ.
Stop
Typ.
Typ.
Represents the start of transmission. Always '1'.
Represents the request type as shown in Figure 7.13.
Represents the address of the PHY register to which data is written.
Represents the PHY register data to be written.
Represents the completion of transmission. Always '0'.
Represents the start of transmission. Always '1'.
Represents the request type as shown in Figure 7.13.
When this bit is '0,' arbitration acceleration can be disabled.
When this bit is '1,' arbitration acceleration can be enabled.
Represents the completion of transmission. Always '0'.
Immediate request
Isochronous request
Priority request
Fair request
Read data from the configured register
Write data in the configured register
Represents that PHY arbitration acceleration is disabled/enabled.
Reserved
Table 7.12 Acceleration control format
Table 7.11 Write register format
Table 7.13 Request type
EPSON
Description
Description
Description
S1R72900F00A
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