s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 42

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

S1R72900F00A
As soon as the reception of a register write request completes, the SIR72900F00A changes the data at the address.
On receiving a register read request, the SIR72900F00A outputs the data at the address to the Link layer controller IC
as a status transmission. If the output is interrupted by packet reception/transmission, the SIR72900F00A repeats the
status output from the first bit until the output completes.
When the SIR72900F00A receives a bus request (FairReq, PriReq, IsoReq or ImmReq), it ignores the next bus request
until the preceding request is canceled by packet reception, packet transmission, or subaction gap (for IsoReq and
ImmReq only).
When the SIR72900F00A receives the next register read request before the preceding register read request completes,
the operation becomes indefinite.
Any bus request is cleared by a bus reset.
The SIR72900F00A automatically sets an Accelerating bit with IsoReq, enabling acceleration arbitration.
7.4.4.2 Status output
The SIR72900F00A outputs information shown in Table 7.14 as a status output to the PHY/LINK interface. The
SIR72900F00A asserts '01b' to the CTL pin and outputs information to the D[0:1] pin. The CTL pin outputs '01b' while
the status output continues.
The SIR72900F00A usually outputs the first four bits (Arbitration Reset Gap, Subaction Gap, Bus Reset, and PHY
interrupt) necessary for the Link state machine as a status output.
However, when it receives a register read request from the Link layer controller IC, it outputs all status information as
a return value. In addition, when the SIR72900F00A has sent its Self-ID packet during the Self-ID period (when its
Physical_ID has been determined), it automatically outputs the PHY register information on address '00h' containing
its Physical_ID to the Link layer controller IC.
Status output may be interrupted by packet reception/transmission. When the status output is interrupted, the
SIR72900F00A repeats the status output according to the following rules.
The SIR72900F00A outputs a status as PHY Interrupt in the following cases.
38
–The information that has been output before the interrupt is cleared and status output is not repeated.
–Status output starts with the S[0:1] bit and is done in the units of 4 bits/16 bits.
–When it detects that the bus is looped.
–When it detects that the cable voltage has dropped.
–When the state machine of the SIR72900F00A has timed out.
–When the Port_event bit has changed to '1'.
8 to 15
Bit(s)
4 to 7
CTL[0:1]
0
1
2
3
D[0:1]
Arbitration Reset Gap
00
00
Subaction Gap
PHY Interrupt
Bus Reset
Address
Data
Typ.
S[0:1]
01
S[2:3]
01
Table 7.14 Status format
S[4:5]
Detects an Arbitration Reset Gap.
Detects a Subaction Gap.
Detects a Bus Reset.
Requests the host for an interrupt.
PHY register address to which the status is returned
Status data
Figure 7.21 Status
01
EPSON
S[6:7]
01
Description
S[14:15]
01
00
00
00
00
Rev. 1.0