s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 14

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

S1R72900F00A
7.1.2.2 Register 1
Bit 0: Root Hold Bit
Bit 1: Initiate Bus Reset
Bits 2 to 7: Gap Count
7.1.2.3 Register 2
Bits 0 to 2: Extended register
Bits 3 to 7: Total of Port
7.1.2.4 Register 3
10
This bit is set automatically by PHY configuration packet transmission.
When this bit is '1', it is a request that the node should be the root at the next bus reset.
Setting this bit immediately issues a bus reset command.
When this bit is '1', a bus reset is issued. This bit is initialized by bus reset.
These bits are also set automatically by PHY Configuration packet transmission indicating Gap Count values. They
retain the value at the first bus reset after configuration, and are initialized at the second bus reset.
The register map that the SIR72900F00A supports. '111b' is read.
The number of ports on the SIR72900F00A. Normally, 2 ('00010b') is read.
Address
Address
Address
0x01
0x03
0x04
0: RHB
1: IBR
2: Gap_count [0]
3: Gap_count [1]
4: Gap_count [2]
5: Gap_count [3]
6: Gap_count [4]
7: Gap_count [5]
0: Max_speed [0]
1: Max_speed [1]
2: Max_speed [2]
3: Reserved
4: Delay [0]
5: Delay [1]
6: Delay [2]
7: Delay [3]
0: LCtrl
1: Contender
2: Jitter [0]
3: Jitter [1]
4: Jitter [2]
5: Power_class [0]
6: Power_class [1]
7: Power_class [2]
Bit Symbol
Bit Symbol
Bit Symbol
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
Power Reset Value
Power Reset Value
Power Reset Value
EPSON
See discription
0
0
1
1
1
1
1
1
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
Root Hold Bit
Initiate Bus Reset
Gap Count_bit0
Gap Count_bit1
Gap Count_bit2
Gap Count_bit3
Gap Count_bit4
Gap Count_bit5
Speed
Speed
Speed
Delay
Delay
Delay
Delay
Link Control
Contender
Jitter
Jitter
Jitter
Power Class
Power Class
Power Class
Description
Description
Description
Rev. 1.0