s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 37

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s1r72900

Manufacturer Part Number
s1r72900
Description
Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
Manufacturer
Epson Electronics America, Inc.
Datasheet

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The S1R72900F00A issues short bus reset (SBR) against other nodes connected when detecting LPS = "1". This
function makes cancellation possible by clearing Page select7Register 70 bit 7. A typical external circuit for the LPS
pin is shown in Figures 7.17, 18 and 19.
* The LPS control signal shown Figure 7.17 is required to be 0.8 V lower when the power supply on the upper layer
compared to the Link layer is set to OFF. For example, if the LPS control signal is output from the Link layer controller
IC, LPS output is required to be GND output when the Link layer controller IC power supply is set to OFF. (For V
output, LPS = "0" may not be recognized because the V
Also, even when the system’s power supply is connected to the LPS pin as shown in Figure 7.18, it is required to be
0.8V lower when the power supply on the upper layer compared to the Link layer is set to OFF. When using a 3.3V
power supply for the Link layer controller IC, pay attention to the LPS connection because the V
become 0.8V lower when the power supply is set to OFF.
Rev. 1.0
Figure 7.18 A typical direct connection and LPS external circuit 2 (without external signal control)
Figure 7.17 A typical direct connection and LPS external circuit 1 (with external signal control)
LPS pin
LPS pin
EPSON
10k
DD
22k
33k
potential may not become 0.8V lower.)
System 5V power supply
LPS control signal
DD
S1R72900F00A
potential may not
DD
33

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