s1r72900 Epson Electronics America, Inc., s1r72900 Datasheet - Page 16

• Manufacturer Part Number: s1r72900
• Description: Physical Layer Ic Compliant With The Ieee 1394-1995 And Ieee 1394a-2000 Standards.
• Manufacturer: Epson Electronics America, Inc.

S1R72900F00A
7.1.2.6 Register 5
Bit 0: Watchdog
Bit 1: Initiate Short (Arbitrated) Bus Reset
Bit 2: Loop detect
Bit 3: Cable power failure detect
Bit 4: Arbitration state machine timeout
Bit 5: Port_event detect
Bit 6: Enable arbitration acceleration
Bit 7: Enable multi-speed packet concatenation
12
When set to '1,' this bit communicates the status of Loop, Power_fail, and Arb_timeout to the Link layer controller
IC, regardless of the status of the PHY/LINK interface. When a resume action starts on any port, this bit sends a
resume interrupt signal regardless of the value of Int_enable.
Setting this bit to '1' issues short bus reset.
This bit is cleared when the short bus reset completes.
When this bit is '1,' the bus is looped.
This bit is cleared when hardware reset occurs or '1' is written.
When this bit is '1,' it means that the PC bit has changed from 1 to 0.
This bit is cleared when '1' is written.
When this bit is '1,' it means that the node had been in a state other than Tree_IDStart longer than
MAX_ARB_STATE_TIME.
This bit is cleared when hardware reset occurs or '1' is written.
When Int_enable is '1,' detection of a change in the Connected, Bias, Disabled, or Fault bit sets this bit to '1.'Also,
when Watchdog is '1,' a Resume process sets this bit to '1.'
This bit is cleared when hardware reset occurs or '1' is written.
Setting this bit to '1' causes Ack-acceleration arbitration and fly-by arbitration. When this bit is set to '0,' no
acceleration arbitration occurs.
This bit is initialized as hardware reset occurs.
When this bit is set to '1,' a joint packet transmission request requires a speed code. When this bit is set to '0,' joint
packet transmission is done at the same speed as the first packet transmission.
This bit is initialized as hardware reset occurs.
Address
0x05
0: Watchdog
1: ISBR
2: Loop
3: Pwr_fail
4: Timeout
5: Port_event
6: Enab_accel
7: Enab_multi
Bit Symbol
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power Reset Value
EPSON
0
0
0
1
0
0
0
0
Watchdog
Initiate Short Bus Reset
Loop detect
Cable power failure detect
Arbtration state machine timeout
Port_event detect
Enable arbitration acceleration
Enable multi-speed packet concatenation
Description
Rev. 1.0