mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 94

• Manufacturer Part Number: mpc8347ecvvalf
• Description: Mpc8347e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Document Revision History
22 Document Revision History
Table 66
94
Revision
10
9
8
7
provides a revision history of this document.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
4/2007
3/2007
2/2007
8/2006
Date
In
added USB to the seventh row.
In
line.
In
In
paragraph, added a new paragraph.
Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
In Table 54, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency ( csb_clk )’
row, changed the value in the 533 MHz column to 100–333.
In Table 60, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK
Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz
CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306, changed
the CORE PLL value to 0000110.
In Section 23, “Ordering Information,” replaced first paragraph and added a note.
In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced first paragraph.
Page 1, updated first paragraph to reflect PowerQUICC II information. Updated note after second
paragraph.
In the features list in Section 1, “Overview,” corrected DDR data rate to show:
In Table 5, “MPC8347E Typical I/O Power Dissipation,” added GV
table footnote to designate rates that apply only to the TBGA package.
In Figure 43, “JTAG Interface Connection,” updated with new figure.
In Section 23, “Ordering
In Section 23.1, “Part Numbers Fully Addressed by This
paragraph directing customer to product summary page for available frequency configuration parts.
Updated back page information.
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed V
OV
In Table 60, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
• 266 MHz for PBGA parts for all silicon revisions
• 333 MHz for DDR for TBGA parts for silicon Rev. 1.x
Figure 20, “Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode),”
Table
Table
Section 21.7, “Pull-Up Resistor Requirements,”
DD
– 0.3.
3,
54,
“Output Drive Capability,”
IH
“Operating Frequencies for TBGA,”
Table 66. Document Revision History
minimum value in Table 36, “JTAG Interface DC Electrical Characteristics,” to
Information,”
changed the values in the Output Impedance column and
Substantive Change(s)
replicated note from document introduction.
added column for 400 MHz.
deleted last two paragraphs and after first
Document,”
DD
1.8-V values for DDR2; added
replaced third sentence of first
Freescale Semiconductor
updated LALE time