mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 76

• Manufacturer Part Number: mpc8347ecvvalf
• Description: Mpc8347e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Clocking
As shown in
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the
csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL),
which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset,
clocking, and initialization in the MPC8349E Reference Manual for more information on the clock
subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (÷2) to
create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the
same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create
the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is
controlled by LCCR[CLKDIV].
In addition, some of the internal units may have to be shut off or operate at lower frequency than the
csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped
register after the device exits reset.
76
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
ddr_clk = csb_clk × (1 + RCWL[DDRCM])
lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
Figure
TSEC1
TSEC2, I
Security Core
USB DR, USB MPH
PCI and DMA complex
40, the primary clock input (frequency) is multiplied up by the system phase-locked
2
C1
Unit
Table 53
Table 53. Configurable Clock Units
specifies which units have a configurable clock frequency.
Frequency
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk/3
Default
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
Options
Freescale Semiconductor