mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 81

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mpc8347ecvvalf

Manufacturer Part Number
mpc8347ecvvalf
Description
Mpc8347e Powerquicc Ii Pro Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
19.3
Table 60
Freescale Semiconductor
Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency
is in the range of 800–1800 MHz.
0–1
nn
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
RCWL[COREPLL]
shows suggested PLL configurations for 33 and 66 MHz input clocks.
Suggested PLL Configurations
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
0000
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
2–5
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
6
n
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Core VCO frequency = core frequency × VCO divider
(PLL off, csb_clk clocks core directly)
Table 59. e300 Core PLL Configuration
core_clk : csb_clk Ratio
PLL bypassed
1.5:1
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
1:1
1:1
1:1
1:1
2:1
2:1
2:1
2:1
3:1
3:1
3:1
3:1
NOTE
(PLL off, csb_clk clocks core directly)
PLL bypassed
VCO Divider
2
4
8
8
2
4
8
8
2
4
8
8
2
4
8
8
2
4
8
8
1
Clocking
81

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