mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 17

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mpc8347ecvvalf

Manufacturer Part Number
mpc8347ecvvalf
Description
Mpc8347e Powerquicc Ii Pro Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet
6.2.2
Table 14
DDR SDRAM interface.
Freescale Semiconductor
At recommended operating conditions with GV
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS(n) output setup with respect to MCK
MCS(n) output hold with respect to MCK
MCK to MDQS
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to
MDQS
and
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
DDR SDRAM Output AC Timing Specifications
Table 15
Parameter
provide the output AC timing specifications and measurement conditions for the
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
DD
of 2.5 V ± 5%.
Symbol
t
t
t
t
t
t
t
t
t
t
DDKHMH
DDKHDS,
DDKHDX,
AOSKEW
DDKHAS
DDKHAX
DDKHCS
DDKHCX
DDKLDS
DDKLDX
t
MCK
1
–1000
–1100
–1200
1200
1200
3.45
2.65
3.45
2.65
–0.9
–1.1
–1.2
Min
900
900
900
900
2.8
4.6
2.0
3.8
2.8
4.6
2.0
3.8
6
Max
200
300
400
0.3
0.5
0.6
10
Unit
ns
ps
ns
ns
ns
ns
ns
ps
ps
DDR SDRAM
Notes
2
4
4
4
4
5
6
6
3
17

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