mpc8347ecvvalf Freescale Semiconductor, Inc, mpc8347ecvvalf Datasheet - Page 78

• Manufacturer Part Number: mpc8347ecvvalf
• Description: Mpc8347e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Clocking
19.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
and
CLKIN/PCI_SYNC_IN ratios.
78
Table 58
System PLL Configuration
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
show the expected frequency values for the CSB frequency for select csb_clk to
Section 19, “Clocking,”
Table 56. System PLL Multiplication Factors
RCWL[SPMF]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
the LBIUCM, DDRCM, and SPMF parameters in the reset
System PLL Multiplication
Reserved
Factor
× 16
× 10
× 11
× 12
× 13
× 14
× 15
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
Table 56
shows the multiplication factor
Freescale Semiconductor
Table 57