mpc82x52a Megawin Technology, mpc82x52a Datasheet - Page 30

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mpc82x52a

Manufacturer Part Number
mpc82x52a
Description
8-bit Micro-controller
Manufacturer
Megawin Technology
Datasheet
30
The 33
interrupt. Neither of these flags is cleared by hardware when the service routine is vectored to.
The service routine should poll them to determine which one to request service and it will be
cleared by software.
All of the bits that generate interrupts can be set or cleared by software with the same result
as done through it by hardware. In other words, interrupts or pending interrupts can be
generated or canceled in software.
The following content describes several SFR related to interrupt mechanism.
SFR: IE(Interrupt Enable)
EA: =Global interrupt controller.
EPCA_LVD: =Interrupt controller of Programmable Counter Array (PCA) and Low-Voltage
ESPI_ADC: = Interrupt controller of Serial Peripheral Interface (SPI) and A/D Converter (ADC).
ES: =Interrupt controller of Universal Asynchronous Receiver/Transmitter (UART).
ET1: =Interrupt controller of Timer-1 interrupt.
EX1: =Interrupt controller of external interrupt-1.
Bit-7
H
EA
interrupt is shared by the logical OR of PCA interrupt and LVD (Low-Voltage Detector)
0: = (default)
1: =
0: = (default)
1: =
0: = (default)
1: =
0: = (default)
1: =
0: = (default)
1: =
0: = (default)
1: =
Disable all interrupts
Release interrupt control to all individual interrupt controllers.
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
EPCA_LVD ESPI_ADC
Detector
Bit-6
Bit-5
MPC82x52A Data Sheet
Bit-4
ES
Bit-3
ET1
Bit-2
EX1
Bit-1
ET0
MEGAWIN
Bit-0
EX0

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