mpc82x52a Megawin Technology, mpc82x52a Datasheet - Page 17

• Manufacturer Part Number: mpc82x52a
• Description: 8-bit Micro-controller
• Manufacturer: Megawin Technology

MEGAWIN
NVM register: OR1 (Option Register 1):
NVM register: OR2 (Option Register 2):
{ISPAS1, ISPAS0}: = ISP-Address-Start
HWBS: = HardWare-Boot-Selector
reserved1:= The bit is reserved for afterward user, and should be left at set.
SB: = Used to decide if the program code will be Scrambled while it is dumped.
LOCK: = Used to decide if the program code will be Locked against the popular writer.
OR1 [7:1]: = Used to set the boundary of IAP memory
reserved1:= The bit is reserved for afterward user, and should be left at set.
reserved1
In fact, the boot entrance is determined by register SWBS from SFR ISPCR ignoring the boot
comes from RST-pin press, software-trigger, or power-up. However, if a boot happens and that
boot comes from power-up action, the device will first load the complement of the HWBS to SWBS,
and decides the boot entrance according to the state of bit SWBS. So the HWBS is named
HardWare Boot Selector. It influence on power-up boot, but not on the boot from RST-pin or
software-trigger.
The user’s application program can change only the IAP flash memory, neither of AP flash
memory itself, nor the ISP flash memory. The IAP memory is defined between address scope
OR1 [7:1]*512 and ISP-Address-Start. Setting the OR1 [7:1] 1111111
Bit-7
Bit-7
{0,0}: =
{0,1}: =
{1,0}: =
{1,1}: = (default)
0: = (default)
1:=
0: =
1: = (default)
0: =
1: = (default)
Set the ISP start address 1400
Set the ISP start address 1800
Set the ISP start address 1C00
Express no ISP code.
Clearing the bit is to configure the device to boot from ISP program after power-up.
Setting the bit is to configure the device to boot normally from user’s application program
after power-up.
Code dump from Writer is scrambled.
Code dump from Writer is transparent.
Code dumping from Writer is locked.
Permit code dumping from general Writers.
The user must not clear the bit; otherwise, there could be inadvertent effect impacted on
the device.
OSCDN
Bit-6
Bit-6
Bit-5
Bit-5
-
MPC82x52A Data Sheet
reserved1
H
H
H
Bit-4
Bit-4
. (ISP code could take 3K bytes)
. (ISP code could take 2K bytes)
. (ISP code could take 1K bytes)
Bit-3
Bit-3
-
reserved1
Bit-2
Bit-2
B
means no IAP memory.
ENROSC
Bit-1
Bit-1
reserved1
Bit-0
Bit-0
-
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