adsp-bf527c Analog Devices, Inc., adsp-bf527c Datasheet - Page 27

• Manufacturer Part Number: adsp-bf527c
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
REGISTER MAP
The complete register map is shown in
description can be found in
vant text of the device description. There are 11 registers with
Table 28. Program Register Mapping
Table 29. Register Descriptions
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R15
Register Address
Register 0
000 0000
Left Line In
Register 1
000 0001
Right Line In
Register 2
000 0010
Left Headphone Out
B15 B14 B13 B12 B11 B10 B9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address
0
0
0
0
0
0
0
0
1
1
1
Bit Label
4:0 LINVOL[4:0] 10111
7 LINMUTE
8 LRINBOTH
4:0 RINVOL[4:0] 10111
7 RINMUTE
8 RLINBOTH
6:0 LHPVOL
7 LZCEN
8 LRHPBOTH
[6:0]
0
0
0
0
1
1
1
1
0
0
1
Table 29 on Page 27
0
0
1
1
0
0
1
1
0
0
1
0 LRINBOTH
1 RLINBOTH
0 LRHPBOTH
1 RLHPBOTH
0
1
0
1
0
1
1
Table
Default Description
( 0 dB )
1
0
( 0 dB )
1
0
1111001
( 0 dB )
0
0
B8
0
0
0
0
0
0
28. The detailed
and in the rele-
Left Channel Line Input Volume Control
11111 = +12 dB in 1.5 dB steps down to 00000 = –34.5 dB
Left Channel Line Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
Left to Right Channel Line Input Volume and Mute Data Load Control
1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE
0 = Disable Simultaneous Load
Right Channel Line Input Volume Control
11111 = +12 dB in 1.5 dB Steps Down to 00000 = –34.5 dB
Right Channel Line Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
Right to Left Channel Line Input Volume and Mute Data Load Control
1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE
0 = Disable Simultaneous Load
Left Channel Headphone Output Volume Control
1111111 = +6 dB in 1 dB Steps Down to 0110000 = –73 dB
0000000 to 0101111 = MUTE
Left Channel Zero Cross Detect Enable
1 = Enable
0 = Disable
Left to Right Channel Headphone Volume, Mute and Zero Cross Data Load Control
1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
CODEC_BCLKINV
Rev. PrC | Page 27 of 44 | June 2008
CLKODIV2
RINMUTE
LINMUTE
PWROFF
RZCEN
LZCEN
B7
0
0
SIDEATT
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
CLKOUTPD OSCPD OUTPD DACPD ADCPD MICPD
CLKIDIV2
MS
B6
0
0
0
0
16-bits per register (7-bit address plus nine bits of data). These
can be controlled using either the two wire USB or three wire
SPI interface.
SIDETONE DACSEL BYPASS INSEL MUTEMIC MICBOOST
LRSWAP
B5
0
0
0
0
RESET
Data
HPOR DACMU
LRP
B4
0
SR
LHPVOL
RHPVOL
B3
0
IWL
B2
LINVOL
RINVOL
0
DEEMPH
BOSR
B1
0
FORMAT
USB/NORM
ADC HPD
LINEINPD
ACTIVE
B0