adsp-bf527c Analog Devices, Inc., adsp-bf527c Datasheet - Page 19

• Manufacturer Part Number: adsp-bf527c
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
LRC. Right channel data immediately follows left channel data.
Depending on word length, CODEC_BCLK frequency and
sample rate—there may be unused CODEC_BCLK cycles
between the LSB of the right channel data and the next sample.
Operating the digital audio interface in frame sync mode makes
support of the various sample rates and word lengths easier. The
only requirement is that all data is transferred within the correct
number of CODEC_BCLK cycles to suit the chosen word
length.
Mark-Space Ratios
For the digital audio interface to offer similar support in the
three other modes (Left Justified, I
DACLRC, ADCLRC and CODEC_BCLK frequencies, continu-
ity and mark-space ratios need careful consideration.
In slave mode the DACLRC and ADCLRC inputs are not
required to have a 50:50 mark-space ratio. The CODEC_BCLK
input need not be continuous. It is however required that there
are sufficient CODEC_BCLK cycles for each
DACLRC/ADCLRC transition to clock the chosen data word
length. The non 50:50 requirement on the LRCs is useful in situ-
DACLRC/
ADCLRC
DACLRC/
ADCLRC
DACDAT/
ADCDAT
CODEC_BCLK
DACDAT/
ADCDAT
CODEC_BCLK
MSB
1
MSB
1
2
1 CODEC_BCLK
INPUT WORD LENGTH (W
1 CODEC_BCLK
3
2
INPUT WORD LENGTH (W
LEFT CHANNEL
3
2
S, and Right Justified), the
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
Figure 22. Frame Sync/PCM Mode Audio Interface (Mode A, LRP=1)
Figure 23. Frame Sync/PCM Mode Audio Interface (Mode B, LRP=0)
n-2 n-1
L
)
n-2 n-1
L
)
LSB
Rev. PrC | Page 19 of 44 | June 2008
n
LSB
n
1
1
2
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
3
2
1/f
1/f S
RIGHT CHANNEL
S
3
RIGHT CHANNEL
ations such as a USB 12 MHz clock. Simply dividing down a 12
MHz clock within the processor to generate LRCs and
CODEC_BCLK will not generate the appropriate DACLRC or
ADCLRC since they will no longer change on the falling edge of
CODEC_BCLK. For example, with the 12 MHz/32k×f
there are 375 CODEC_MCLK per LRC. In these situations
DACLRC/ADCLRC can be made non 50:50.
In master mode, DACLRC and ADCLRC will be output with a
50:50 mark-space ratio with the CODEC_BCLK output at 64x
base frequency (that is, 48 kHz). The exception again is in USB
mode where CODEC_BCLK is always 12 MHz. For example in
12 MHz/32k×f
period. Therefore DACLRC and ADCLRC outputs will have a
mark space ratio of 187:188.
n-2 n-1
RIGHT CHANNEL
RIGHT CHANNEL
n-2 n-1
n
S
mode there are 375 master clocks per DACLRC
n
S
mode