adsp-bf527c Analog Devices, Inc., adsp-bf527c Datasheet - Page 20

• Manufacturer Part Number: adsp-bf527c
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
Mode Configuration
The ADC and DAC digital audio interface modes are software
configurable as indicated in
software format may result in erroneous operation of the inter-
faces and is therefore not recommended.
Table 14. Digital Audio Interface Control
The length of the digital audio data is programmable at 16-, 20-,
24-, or 32-bits in the I
signed two’s complement. Both ADC and DAC are fixed at the
same data length. The ADC and DAC digital filters process data
using 24-bits. If the ADC is programmed to output 16-bit or 20-
bit data then it strips the LSBs from the 24-bit data. If the ADC
is programmed to output 32-bits then it packs the LSBs with
zeros. If the DAC is programmed to receive 16-bit or 20-bit
data, the CODEC packs the LSBs with zeros. If the DAC is pro-
grammed to receive 32-bit data, then it strips the LSBs.
The DAC outputs can be swapped under software control using
LRP and LRSWAP. Stereo samples are normally generated as a
left/right sampled pair. LRSWAP reverses the order so that a left
sample goes to the right DAC output and a right sample goes to
the left DAC output. LRP swaps the phasing so that a right/left
sampled pair is expected and preserves the correct channel
phase difference.
Register
Address
0000111 1:0 FORMAT[1:0] 10
Bit Label
3:2 IWL[1:0]
4
5
6
7
LRP
LRSWAP
MS
BCLKINV
2
S or left justified modes only. The data is
Table
Default Description
10
0
0
0
0
14. Dynamically changing the
Audio Data Format Select
11 = Frame Sync Mode, Frame Sync Plus Two Data Packed Words
10 = I
01 = MSB First, Left Justified
00 = MSB First, Right Justified
Input Audio Data Bit Length Select
11 = 32-bits
10 = 24-bits
01 = 20-bits
00 = 16-bits
DACLRC phase control (in left, right or I
1 = Right Channel DAC data when DACLRC high
0 = Right Channel DAC data when DACLRC low (opposite phasing in I
or Frame Sync mode A/B select (in Frame Sync mode only)
1 = MSB is available on second CODEC_BCLK rising edge after DACLRC rising
edge
0 = MSB is available on first CODEC_BCLK rising edge after DACLRC rising edge
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
1 = Invert CODEC_BCLK
0 = Do Not Invert CODEC_BCLK
2
S Format, MSB First, Left Justified
Rev. PrC | Page 20 of 44 | June 2008
To accommodate system timing requirements the interpreta-
tion of CODEC_BCLK may be inverted. This is especially
appropriate for Frame Sync mode.
ADCDAT lines are always outputs. They power up and return
from standby low.
DACDAT is always an input. It is expected to be set low by the
audio interface controller when the CODEC is powered off or in
standby.
ADCLRC, DACLRC and CODEC_BCLK can be either outputs
or inputs depending on whether the CODEC is configured as a
master or slave. If the device is a master then the DACLRC and
CODEC_BCLK signals are outputs that default low. If the
device is a slave then the DACLRC and CODEC_BCLK are
inputs. It is expected that these are set low by the audio interface
controller when the CODEC is powered off or in standby.
If right justified 32-bit mode is selected then the CODEC
defaults to 24-bits.
2
S modes)
Preliminary Technical Data
2
S mode)