adsp-bf527c Analog Devices, Inc., adsp-bf527c Datasheet - Page 25

• Manufacturer Part Number: adsp-bf527c
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
TWI Mode
The CODEC can be controlled using a 2-wire TWI serial inter-
face. CSDA is used for serial data and CSCL is used for the serial
clock. The device operates as a slave device only. The CODEC
To control the CODEC using the TWI bus, the master control
device initiates a data transfer by establishing a start condition.
This is defined by a high-to-low transition on CSDA while
CSCL remains high, which indicates that an address and data
transfer will follow. All peripherals on the TWI bus respond to
the start condition and shift in the next eight bits (7-bit address
plus read/write bit). The transfer is MSB first. The 7-bit address
consists of a 6-bit base address plus a single programmable bit
to select one of two available addresses for this device (see
Table 24 on Page
read/write bit is ‘0’, indicating a write, the CODEC responds by
pulling CSDA low on the next clock pulse (ACK). The CODEC
is a write only device and will only respond when the read/write
bit indicates a write. If the address is not recognized, the
CODEC returns to the idle condition and waits for a new start
condition and valid address.
Table 24. TWI Address Selection
Once the CODEC has acknowledged a correct address, the con-
troller sends eight data bits ([B15:B8]). The CODEC then
acknowledges the data by pulling CSDA low for one clock pulse.
The controller then sends the remaining eight data bits
([B7:B0]) and the CODEC then acknowledges again by pulling
CSDA low.
A stop condition is defined when there is a low-to-high transi-
tion on CSDA while CSCL is high. If a start or stop condition is
detected out of sequence at any point in the data transfer then
the device jumps to the idle state.
After receiving a complete address and data sequence the
CODEC returns to the idle state and waits for another start con-
dition. Each write to a register requires the complete sequence
of start condition, device address, and read/write bit followed by
the 16-bit register address and data.
CSB State
0
1
CSCL
CSDA
Address
0011010
0011011
25). If the correct address is received and the
START
R ADDR
R/W
Rev. PrC | Page 25 of 44 | June 2008
ACK
Figure 27. TWI Interface
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
CONTROL ADDRESS
DATA B15-8
has one of two slave addresses that are selected by setting the
state of pin 15, (CSB). The TWI interface protocol is shown in
Figure
POWER DOWN MODES
The CODEC contains power conservation modes where various
circuit blocks may be safely powered down. These modes are
software programmable as shown in
Table 25. Power Conservation Mode Control
Register
Address
000 0110 0
26.
ACK
Bit Label
1
2
3
4
5
6
7
LINEINPD
MICPD
ADCPD
DACPD
OUTPD
OSCPD
CLKOUTPD 0
POWEROFF 1
CONTROL DATA
DATA B7-0
Default Description
1
1
1
1
1
0
Table
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
Microphone Input and
Bias Power Down
1 = Enable Power Down
0 = Disable Power Down
ADC Power Down
1 = Enable Power Down
0 = Disable Power Down
DAC Power Down
1 = Enable Power Down
0 = Disable Power Down
Line Output Power Down
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
CODEC_CLKOUT power
down
1 = Enable Power Down
0 = Disable Power Down
Power Off Device
1 = Device Power Off
0 = Device Power On
ACK
25.
STOP