adsp-bf527c Analog Devices, Inc., adsp-bf527c Datasheet - Page 24

• Manufacturer Part Number: adsp-bf527c
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
The actual sample rates achieved are shown in
Table 20. USB Mode Sample Rate Look-up
1
Table 21. USB Mode Actual Sample Rates
Sampling Rate
(kHz)
ADC
48
44.118 44.118 12.000
48
44.118 8.021
8
8.021
8
8.021
32
96
88.235 88.235 12.000
Target
Sampling
Rate
8 kHz
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
Other combinations of BOSR and SR[3:0] are not valid
CSCL
CSDA
DAC
48
8.021
48
44.118 12.000
8
8.021
32
96
CSB
8 kHz
32 kHz
n/a
48 kHz
n/a
96 kHz
Actual Sampling Rate
BOSR = 0 ( 250 × f
12 MHz/(250 x 48/8)
12 MHz/(250 x 48/32)
12 MHz/250
12 MHz/125
CODEC_MCLK
Frequency
(MHz)
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
NOTE: CSB IS EDGE SENSITIVE NOT LEVEL SENSITIVE. THE DATA IS LATCHED ON THE RISING EDGE OF CSB.
B15
B14
S
) BOSR = 1 (272 × f
Sample Rate Register
Setting
BOSR SR3 SR2 SR1 SR0
0
1
0
1
0
1
0
1
0
0
1
8.021 kHz
12 MHz/(272 x 11/2)
n/a
44.117 kHz
12 MHz/272
n/a
88.235 kHz
12 MHz/136
n/a
B13
CONTROL ADDRESS
0
1
0
1
0
1
0
1
0
0
1
1
B12
0
0
0
0
0
0
0
0
1
1
1
Table
0
0
0
0
1
1
1
1
1
1
1
B11
Rev. PrC | Page 24 of 44 | June 2008
S
21.
)
0
0
1
1
0
0
1
1
0
1
1
B10
Figure 26. SPI Interface
Digital
Filter
Type
0
1
0
1
0
1
0
1
0
3
2
B9
B8
Activating the Digital Audio Interface
To prevent communication problems, the audio interface is dis-
abled (three-state with a 100 kΩ pulldown) while the interface
and sampling control are being programmed. Once pro-
grammed, the interface is activated by setting the ACTIVE bit
shown in
Before changing the digital audio interface or sampling control
register the ACTIVE bit should be reset then set.
Table 22. Activating the Audio Interface
SOFTWARE CONTROL INTERFACE
Software control can use either a 3-wire (SPI-compatible) or 2-
wire (TWI) interface. The interface is selected by setting the
CMODE pin shown in
Table 23. Control Interface CMode Selection
In SPI mode, CSDA is used for serial data and CSCL is used for
the serial clock. In TWI mode, the state of the CSB pin allows
the programmer to select one of two addresses.
SPI Mode
The CODEC can be controlled using an SPI serial interface.
CSDA is used for the program data, CSCL is used to clock in the
program data and CSB is used to latch the program data. The
SPI interface protocol is shown in
Register Address Bit Label
000 1001
CMODE
0
1
B7
Table
B6
22.
CONTROL DATA
B5
0
Interface format
TWI
SPI
Preliminary Technical Data
Table
ACTIVE 0
B4
23.
B3
Default Description
Figure
B2
26.
Activate Interface
1 = Active
0 = Inactive
B1
B0