tda933xh NXP Semiconductors, tda933xh Datasheet - Page 39
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tda933xh
Manufacturer Part Number
tda933xh
Description
Tda933xh Series I2c-bus Controlled Tv Display Processors
Manufacturer
NXP Semiconductors
Datasheet
1.TDA933XH.pdf
(56 pages)
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Philips Semiconductors
2002 Jun 04
handbook, full pagewidth
I
Video signals are shown as illustration only. All horizontal timing signals in the IC are solely related to the start of the H
that is applied to the IC.
All horizontal timing signals are generated with the help of the internal line locked clock (LLC). One line period is always divided
into 440 line locked clock pulses. Time periods depicted in the figure are only valid for line frequencies mentioned.
2
C-bus controlled TV display processors
(f H = 31.47 kHz)
(f H = 33.75 kHz)
2f H NTSC
CLP pulse
CLP pulse
H D input
H D input
blanking
blanking
counter
counter
signal
HDTV
signal
Fig.11 Timing of clamp pulse and line blanking in 2f
16 LLC
16 LLC
14 LLC
0.75 s
14 LLC
(a) Timing in 2 f H TV mode (HDTV = 0, HDCL = 0)
(b) Timing in HDTV mode (HDTV = 1, HDCL = 1)
40 LLC = 2.89 s
40 LLC = 2.69 s
0.606 s
50 ns
0.592 s
HSHIFT
37 LLC = 2.67 s
39
2.35 s
15 LLC = 1.01 s
0.592 s
HSHIFT
mid blank = mid flyback
mid blank = mid flyback
5.5 s
3.784 s
H
TV mode and HDTV mode.
18 LLC = 1.22 s
1.993 s
22 LLC = 1.59 s
2.40 s
TDA933xH series
D
pulse
Preliminary specification
MGS897
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