tda933xh NXP Semiconductors, tda933xh Datasheet - Page 34

• Manufacturer Part Number: tda933xh
• Description: Tda933xh Series I2c-bus Controlled Tv Display Processors
• Manufacturer: NXP Semiconductors

Philips Semiconductors
43. The IC has protection inputs for flash protection and overvoltage protection.
44. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason, an extra DAC
45. The vertical scroll function is active only in the expand mode of the vertical zoom, i.e. at a DAC position larger
46. With the vertical wait function, the start of the vertical scan can be delayed with respect to the incoming vertical sync
47. In the TDA9330H and TDA9332H, the DAC output is I
Table 55 Operation of the vertical wait function
2002 Jun 04
1f
2f
2f
1f
2f
I
H
H
H
H
H
2
a) The flash protection input is used to switch the horizontal drive output off immediately if a picture tube flashover
b) The overvoltage (X-ray) protection is combined with the EHT compensation input. When this protection is
is included in the vertical amplitude control, which controls the vertical scan amplitude between 0.75 and 1.38 of the
nominal scan. At an amplitude of 1.05 times the nominal scan, the output current is limited and the blanking of the
RGB outputs is activated, see Fig.14. In addition to the variation of the vertical amplitude, the picture can be vertically
shifted on the screen via the ‘scroll’ function. The nominal scan height must be adjusted at a position of 19H (25 DEC)
of the vertical ‘zoom’ DAC and 1FH (31 DEC) for the vertical ‘scroll’ DAC.
than 10H (16 DEC).
pulse. The operation is different for the various scan modes, see Table 55 and Figs 12 and 13. The minimum value
for the vertical wait is 8 line periods. If the setting is lower than 8, the wait period will remain 8 line periods.
is proportional to the centre frequency of the line-oscillator. In TV mode, the output voltage will always be at the
minimum value. In VGA mode, the output is at the minimum value for the lowest centre frequency (32 kHz) and at
the maximum value for the highest centre frequency (48 kHz). The output impedance of the DAC output depends on
the output voltage. The output consists of an emitter follower with an internal resistor of 50 k to ground.
; TV mode
; TV mode; VSR = 0
; TV mode; VSR = 1
; multi sync mode
; multi sync mode
C-bus controlled TV display processors
occurs, to protect the line output transistor. An external flash detection circuit is needed. When the flash input is
pulled HIGH, the horizontal output is switched off and status bit FLS is set. When the input turns LOW again, the
horizontal output is switched on immediately without I
activated, the horizontal drive can be directly switched off (via the slow stop procedure). It is also possible to
continue the horizontal drive and only set status bit XPR in output byte 01 of the I
two modes of operation is made via bit PRD.
MODE
2
34
C-bus controlled. In the TDA9331H, the DAC output voltage
fixed; see Fig.12
end of V
start of V
start of V
start of V
2
C-bus intervention via the slow start procedure.
D
D
D
D
plus vertical wait setting
plus vertical wait setting
plus vertical wait setting
plus vertical wait setting
START OF VERTICAL SCAN
2
C-bus. The choice between the
TDA933xH series
Preliminary specification