tda933xh NXP Semiconductors, tda933xh Datasheet - Page 14

• Manufacturer Part Number: tda933xh
• Description: Tda933xh Series I2c-bus Controlled Tv Display Processors
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 26 Multi-sync mode
Table 27 Extended slow start mode
Table 28 Long blanking mode
Table 29 Vertical free-running frequency in TV mode
Table 30 De-interlace phase
Table 31 Switch-off in vertical overscan
Table 32 Select vertical frequency
Table 33 Enable vertical guard (RGB blanking)
2002 Jun 04
LBM
OSO
VGA
EVG
I
ESS
SVF
VFF
DIP
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C-bus controlled TV display processors
delay of 1st field (start of synchronized V
pulse coincides with H-flyback) with 0.5 H
fixed in accordance with 50 Hz standard
50 Hz (SVF = 0) or 100 Hz (SVF = 1)
60 Hz (SVF = 0) or 120 Hz (SVF = 1)
horizontal frequency fixed by internal
EXTENDED SLOW START MODE
vertical frequency is 100 or 120 Hz
adapted to standard (50 or 60 Hz)
vertical frequency is 50 or 60 Hz
multi-sync function switched on
switch-off in vertical overscan
delay of 2nd field with 0.5 H
VERTICAL GUARD MODE
switch-off undefined
BLANKING MODE
FREQUENCY
not active
not active
reference
PHASE
MODE
MODE
MODE
active
active
D
14
Table 34 Interlace
Table 35 Soft clipping level
Table 36 Clamp pulse timing
Note
1. See Chapter “Characteristics”; note 13.
Table 37 Start line blanking (15 steps; 2 line locked clock
Note
1. See Chapter “Characteristics”; note 13.
Output status bits
Table 38 Power-on reset
Table 39 Field frequency indication
HDCL
LBL3
POR
SC1
FSI
DL
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
period per step; 1 line period is 440 LLC pulses)
LBL2
SC0
0
1
0
1
0
1
1
BETWEEN SOFT CLIPPING AND
LBL1
0
1
1
VOLTAGE DIFFERENCE
FREQUENCY
normal timing
HDTV timing
50 or 100 Hz
60 or 120 Hz
power-down
de-interlace
TDA933xH series
STATUS
MODE
interlace
10% above PWL
normal
MODE
0% above PWL
5% above PWL
LBL0
soft clipping off
0
1
1
Preliminary specification
PWL
(1)
BLANKING
START LINE
+14 LLC
normal
16 LLC
(1)