tda933xh NXP Semiconductors, tda933xh Datasheet - Page 30

• Manufacturer Part Number: tda933xh
• Description: Tda933xh Series I2c-bus Controlled Tv Display Processors
• Manufacturer: NXP Semiconductors

Philips Semiconductors
13. The timing of the horizontal blanking pulse on the RGB outputs is illustrated in Fig.10.
14. When a YUV or RGB signal is applied to the IC and no separate horizontal or vertical timing pulses are available, an
15. Start-up behaviour of the CCC loop. After the horizontal output is released via bits STB, the RGB outputs are blanked
16. Voltage V
17. Signal-to-noise ratio (S/N) is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 10 MHz).
18. This is a current input. When the black current feedback loop is closed (only during measurement lines or during fixed
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a) The start of the blanking pulse is determined by an internal counter blanking that starts 40 LLC (line locked clock)
b) When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by reducing the horizontal scan
external sync separator circuit is needed. The TDA933xH has an edge triggered phase detector circuit on the H
input that uses the start of the H
vertical blanking period, it is important that the sync separator does not generate extra horizontal sync pulses during
the vertical sync pulse on the video signal.
and the CCC loop is activated. Because the picture tube is cold, the measured cathode currents are too small, and
both gain and offset are set at the maximum value so that the CCC loop gets out of range and status bit BCF is set
to 1. Once the picture tube is warm, the loop comes within range and the set signal for bit BCF is removed. Status
bit BCF is set if the voltage of at least one of the cut-off measurement lines at the RGB outputs is lower than 1.5 V
or higher than 3.5 V. The RGB outputs are unblanked as soon as bit BCF changes from 1 to 0. To avoid a bright
picture after switch-on with a warm picture tube, reset of bit BCF is disabled for 0.5 s after switch-on of the horizontal
output. If required, the blanking period of the RGB outputs can be increased by forcing the blanking level at the RGB
outputs via RBL = 1. When status bit BCF changes from 1 to 0, bit RBL can be set to 0 after a certain waiting period.
lowest of the three RGB output voltages during the cut-off measurement lines is within the alignment window of
a) Voltage V
b) It should be noted that bit WBC is only meant for factory alignment of voltage V
beam current switch off), the voltage at this pin is clamped at 3.3 V. When the loop is open circuit, the input is not
clamped and the maximum sink current is approximately 100 A. The voltage on the pin must not exceed the supply
voltage.
C-bus controlled TV display processors
0.1 V around 2.5 V. Bit HBC is 0 if the lowest cut-off level is below 2.6 V, and 1 if this level is above 2.6 V.
pulses before the centre of the horizontal flyback pulse. This is 5.8 s for 1fH and 2.9 s for 2fH TV mode. The
end of the blanking is determined by the trailing edge of the flyback pulse. If required, the start of the counter
blanking can be adjusted in 15 steps with bus bits LBL3 to LBL0. This can be useful when HDTV or VGA signals
are applied to the IC.
amplitude, the edges of the picture may be slightly disturbed. This effect can be prevented by adding an additional
blanking pulse to the RGB signals. This blanking pulse is derived from the horizontal oscillator and is directly
related to the incoming H
normal blanking signal by approximately 1 s (1f
by bit HBL. The phase of this blanking can be controlled in 15 steps by bits HB3 to HB0.
voltage V
V
be adjusted higher until bit WBC becomes 1.
on the video content, this is not a problem. Correct operation of the black current loop is guaranteed as long as
status bit BCF = 0, meaning that the DC level of the measurement lines at the RGB outputs of the IC is between
1.5 and 3.5 V.
g2
should be adjusted lower until bit WBC becomes 1. If HBC = 1, the DC level is too high and voltage V
g2
of the picture tube can be aligned with the help of status bits WBC and HBC. Bit WBC becomes 1 if the
g2
g2
should be adjusted. If bit HBC = 0, the DC level at the RGB outputs of the IC is too low and voltage
should be aligned such that bit WBC becomes 1. If bit WBC is 0, bit HBC indicates in which direction
D
pulse (independent of the flyback pulse). The additional blanking pulse overlaps the
D
pulse as timing reference. To avoid horizontal phase disturbances during the
H
) or 0.5 s (2f
30
H
) on both sides. This wide blanking is activated
g2
. If the value of bit WBC depends
TDA933xH series
Preliminary specification
g2
should
D