tda933xh NXP Semiconductors, tda933xh Datasheet - Page 33

• Manufacturer Part Number: tda933xh
• Description: Tda933xh Series I2c-bus Controlled Tv Display Processors
• Manufacturer: NXP Semiconductors

Philips Semiconductors
35. For safe operation of the horizontal output transistor and to obtain a controlled switch-on time of the EHT, the
36. This parameter is not tested during production and is just given as application information for the designer of the
37. The rise and fall times of the blanking pulse and clamping pulse at the sandcastle output (pin 9) depend on the
38. The vertical guard pulse from the vertical output stage should be connected to pin 9 which acts as a current sense
39. Switching between the 1f
40. The vertical linearity is measured on the differential output current at the vertical drive output (pins 1 and 2) for zero
41. The field detection mechanism is explained in Fig.17.
42. Output range percentages mentioned for E-W control parameters are based on the assumption that the E-W
2002 Jun 04
I
2
horizontal drive starts up in a slow start mode. The horizontal drive starts with a very short ‘on-time’ of the horizontal
output transistor (line locked clock pulse, i.e. 72 ns), the ‘off-time’ of the transistor is identical to the ‘off-time’ in normal
operation. The starting frequency during switch-on is therefore approximately twice the normal value. The t
slowly increased to the nominal value in approximately 160 ms (see Fig.15). When the nominal frequency is reached,
the PLL is closed such that only very small phase corrections are necessary. This ensures safe operation of the
output stage.
a) For picture tubes with Dynamic Astigmatic Focusing (DAF) guns, the rise of the EHT voltage between
b) During switch-off, the slow-stop function is active. This is realized by decreasing the t
c) The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched
television receiver.
capacitive load. The value of the source current during the rising edge or sink current during the falling edge is
0.7 mA (typical value).
input. The guard pulse should fall within the vertical blanking period (see Figs 12 and 13) and should have a width
of at least one line period. The guard current value should be at least 1 mA.
S-correction. The linearity is defined as the ratio of the upper and lower half amplitudes at the vertical output. The
upper amplitude is measured between lines 27 and 167, the lower amplitude between lines 167 and 307 for a 50 Hz
video signal.
a) The incoming V
b) If bus bit VSR = 0, the end of the V
modulator is dimensioned such that 400 A variation in E-W output current of the IC is equivalent to 20% variation
in picture width. In VGA mode, the E-W output current is proportional to the applied line frequency.
C-bus controlled TV display processors
75 and 100% is preferred to be even slower than the rise time from 0 to 75%. This can be realized by activating
bit ESS, at which the total switch-on time of the horizontal output pulse is approximately 1175 ms.
complementary to the start-up behaviour. The switch-off time is approximately 50 ms. The slow-stop procedure
is synchronized to the start of the first new vertical field after reception of the switch-off command. During the
slow-stop period, the fixed beam current switch-off can be activated (see also note 23). This current is active
during a part of the slow stop period, see Fig.15.
on during the flyback pulse. This protection is not active during the switch-on or switch-off period.
pulse. If the synchronized V
HBLNK, then this is field 1. If the synchronized V
CK2H and HBLNK are both output signals of the horizontal divider circuit that is part of the line-locked clock
generator. A reliable field detection is important for correct interlacing and de-interlacing and for the correct timing
of the measurement lines of the black current loop. For the best noise margin, the edges of the V
be on approximately
If VSR = 1, the starting edge is used.
D
pulse is synchronized with the internal clock signal CK2H that is locked to the incoming H
1
V
4
or the 2f
and
D
3
4
pulse of a field coincides with the internally generated horizontal blanking signal
of the line, referred to the rising edges of the H
V
mode is realized via bit SVF.
D
pulse is used as reference for both field detection and start of vertical scan.
D
pulse does not coincide with HBLNK, then this is field 2. Signals
33
D
input signal.
TDA933xH series
on
Preliminary specification
of the output transistor
D
pulse should
on
is
D