adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 39

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

LVDS Input Clock – Hysteresis
Address:
Attributes
Description
Default
Bit
7:6
5
4
3
2
1
0
b[7]
0
Reserved
Reserved. Write as zero for future compatibility.
INVCLK: Invert Input Reference Clock. This bit is used to invert the input clock.
100HYS: Enable 100mV hysteresis. This bit enables 100mV hysteresis. It should be used for a CMOS
input clock only.
50HYS: Enable 50mV hysteresis. This bit enables 50mV hysteresis. It should be used for a CMOS
input clock only.
20HYS: Enable 20mV hysteresis. This bit enables 20mV hysteresis. It should be used for an LVDS
input clock only.
10HYSOFF: Disable 10mV hysteresis. 10mV hysteresis is the default setting. This bit is used to
disable 10mV hysteresis, in the case where another hysteresis setting is desired, for example when
using a CMOS input clock.
HYSOFF: Disable all hysteresis settings. This bit is used to disable all hysteresis settings.
0
1
0
1
0
1
0
1
0
1
0
1
b[6]
0
0Ah
Write Only.
Register 0Bh reads back contents of register 0Ah.
Reference input clock not inverted.
Reference input clock inverted.
Normal operation (10mV hysteresis)
100mV hysteresis (CMOS input clock only)
Normal operation (10mV hysteresis)
50mV hysteresis. (CMOS input clock only)
Normal operation (10mV hysteresis)
20mV hysteresis. (LVDS input clock only)
10mV hysteresis. (LVDS input clock only)
10mV hysteresis disabled.
Normal operation (10mV hysteresis)
All hysteresis settings disabled.
INVCLK
b[5]
0
100HYS
b[4]
0
39
50HYS
b[3]
Description
0
20HYS
b[2]
0
10HYS
OFF
b[1]
0
HYSOFF
b[0]
0
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