adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet
adc12eu050eb
Related parts for adc12eu050eb
adc12eu050eb Summary of contents
Page 1
... The ADC12EU050 can operate entirely from a 1.2V supply, although a separate output driver supply 1.8V can be used. The device operates from -40 to +85 °C and is supplied © 2009 National Semiconductor Corporation ADC12EU050 Features ■ Xignal ™ CT ■ ...
Page 2
Block Diagram www.national.com 2 30051102 ...
Page 3
... Connection Diagram Ordering Information ≤ Industrial (−40°C ADC12EU050CIPLQ ADC12EU050EB ≤ T +85° 30051101 Package 68 Pin LLP Evaluation Board www.national.com ...
Page 4
Pin Descriptions Pin No. Name ANALOG I ...
Page 5
Pin No. Name 15 DO0+ 16 DO0- 18 DO1+ 19 DO1- 20 DO2+ 21 DO2- 23 DO3+ 24 DO3- 25 DO4+ 26 DO4- 28 DO5+ 29 DO5- 31 DO6+ 32 DO6- 33 DO7+ 34 DO7- 36 BCLK+ 37 BCLK- 38 ...
Page 6
Absolute Maximum Ratings 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Supply Voltage ( Voltage at Analog Inputs ...
Page 7
Symbol Parameter H2 Second Harmonic Distortion H3 Third Harmonic Distortion SFDR Spurious Free Dynamic Range IMD Intermodulation Distortion Dynamic Converter Characteristics – Instant Overload Recovery (IOR) On SNR Signal-to-Noise Ratio(Note 5) Signal-to-Noise and Distortion(Note SINAD 5) ENOB Effective Number of ...
Page 8
Symbol Parameter Inter-channel Characteristics Channel to channel gain match Inter-channel Isolation Reference And Analog Input Characteristics V Full Scale Analog Input Voltage IN Maximum Input for Instantaneous Recovery from Overload R Differential Input Impedance IN V Internal Input Common Mode ...
Page 9
Digital Decimation Filter Characteristics Unless otherwise specified, the following conditions apply 5pF; 100Ω terminated at the receiver; f apply for T = +25°C. A Symbol Parameter Pass Band Pass Band Transition Pass Band Ripple Stop Band Begin Stop ...
Page 10
External Input Clock and PLL Characteristics Unless otherwise specified, the following conditions apply 5pF; 100Ω terminated at the receiver; f apply for T = +25°C. A Symbol Parameter External Input Clock f Allowed input clock frequency CLK t ...
Page 11
Digital Input and Output Characteristics Unless otherwise specified, the following conditions apply 5pF; 100Ω terminated at the receiver; f apply for T = +25°C. A Symbol Parameter Digital Inputs ( SLEEP, RST) DATA ...
Page 12
AC and Timing Characteristics Unless otherwise specified, the following conditions apply 5pF; 100Ω terminated at the receiver; f apply for T = +25°C. A Symbol Parameter General ADC Output Timing Parameters f Sample Rate s Conversion Latency t ...
Page 13
AC and Timing Characteristics (Serial Interface) Unless otherwise specified, the following conditions apply 5pF; 100Ω terminated at the receiver; f apply for T = +25°C. A Symb Parameter ol Serial Interface t S setup time SSELS SEL t ...
Page 14
Timing Diagrams www.national.com FIGURE 1. LVDS/SLVS Output Timing FIGURE 2. Output Level Definitions 14 30051103 30051129 ...
Page 15
FIGURE 3. SPI Write Timing FIGURE 4. SPI Read Timing 15 30051104 30051105 www.national.com ...
Page 16
Typical Performance Characteristics V = 1.2V 1.2V internal REF Units for SFDR and Distortion are dBc. DNL Spectral Response @ f =10MHz Spectral Response @ f =10MHz www.national.com Unless ...
Page 17
Typical Performance Characteristics V = 1.2V 1.2V internal REF Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR vs f CLK SNR, SINAD, SFDR vs f CLK SNR, SINAD, SFDR vs VA, ...
Page 18
Typical Performance Characteristics V = 1.2V 1.2V internal REF Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR vs VA, f SNR, SINAD, SFDR vs Temperature, f SNR, SINAD, SFDR vs Temperature, ...
Page 19
Typical Performance Characteristics V = 1.2V 1.2V internal REF Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR CLK SNR, SINAD, SFDR ...
Page 20
Typical Performance Characteristics V = 1.2V 1.2V internal REF Units for SFDR and Distortion are dBc. SNR, SINAD, SFDR Spectral Response @ f = 9.6MHz, f IN1 Histogram ...
Page 21
Functional Description The ADC12EU050 employs a number of unique strategies to provide a high performance multi-channel ADC that offers a significant power consumption reduction when compared to compteting architectures, as well as easing system level de- sign. The ultra-low power ...
Page 22
There is no ringing and recovery from overload is instantaneous. 1.3 INTEGRATED PRECISION LC PLL The ADC12EU050 family includes an integrated high perfor- mance “clean up” phase locked loop (PLL), simplifying the need for a low jitter external clock. ...
Page 23
Such steep digital filters introduce group delay problems, but the ADC12EU050 includes a digital equalizer, which reduces group delay ripple variation to less than 0.05 samples. In ap- plications where group delay is not of concern, the equalizer can be ...
Page 24
Application Information 2.0 POWER-UP SEQUENCE The ADC12EU050 has three separate power supplies: Ana- log (V ), Digital (V ) and the output drive voltage ( ADC contains a power on reset circuit, connected to VA, and so ...
Page 25
On the input clock, excessive RMS jitter within the PLL band- width will be seen in the output spectrum as sidebands, or close in phase noise, around the fundamental signal. Input Clock Selection For systems which do not have a ...
Page 26
Input Coupling and Common Mode The ADC12EU050 internally generates a common mode of 0.62V possible to provide input signals with other com- mon modes however, the full scale input range of the ADC must be kept in mind. ...
Page 27
Output Modes And Output Common Mode Three different output modes are also supported: SLVS, LVDS and reduced common mode LVDS. SLVS and LVDS modes output data according to their respective specifica- tions. Reduced common mode LVDS must be used when ...
Page 28
FIGURE 18. Output Driver Circuit: SLVS 2.6 USING IOR MODE As discussed in the Functional Description, IOR mode pro- vides instantaneous recovery from overload conditions, with www.national.com As well as the different output modes, the output drive current can also ...
Page 29
The recommended way to enable IOR mode is by setting bit 4 (IOR) of the Modulator Overload Control register (04h). Set- ting this bit will enable IOR mode with the default settings for DGF in the Decimator Clipping Control register ...
Page 30
... If the system requires regulators to provide the ADC12EU050 1.2V operating voltage, National Semiconductor recom- mends the LP3878SD-ADJ Low Noise “Ceramic Stable” Ad- justable Regulator or the LP3879 Low Noise “Ceramic Stable” Regulator. Datasheets for both parts are available from the National Semiconductor website. 30 30051122 ...
Page 31
FIGURE 23. ADC12EU050 Application Diagram 31 30051110 www.national.com ...
Page 32
Programming Guide 3.0 THE SERIAL CONTROL INTERFACE The ADC12EU050 provides several user controlled functions which are accessed through a standard SPI compatible, 3 wire Serial Interface, as shown in the diagram below. Wired OR mode is supported in order to ...
Page 33
The eight address bits, A[7:1] + R/W, are sent first. The data, D[7:0], is then sent for a write transaction, or D[7:0] is received for a read transaction. Address and data are sent and re- ceived with the most-significant-bit (MSB) ...
Page 34
Register Index Address b[7] b[6] Top Control Register 00h Reserved Reserved ADC / LVDS Channel Power Down Register 02h PD7 PD6 Modulator Overload Control Register 04h Reserved Reserved PLL Control Register 08h Reserved Reserved LVDS Input Clock Hysteresis 0Ah Reserved ...
Page 35
Top Control Register Address: 00h Attributes Write Only. Register 01h reads back contents of register 00h, if CBR is set. The Top Control Register is the basic initialization and control register for the device. b[7] Description Reserved Default 0 Bit ...
Page 36
ADC / LVDS Channel Power Down Register Address: Attributes The ADC/LVDS Channel Power Down Register provides the capability to independently power down each ADC channel. b[7] b[6] Description PD7 PD6 Default 0 0 Bit 7 PD7: Power Down Channel 7 ...
Page 37
Modulator Overload Control Register Address: 04h Attributes Write Only. Register 05h reads back contents of register 04h. b[7] b[6] Description Reserved Default 0 0 Bit 7:5 Reserved. Write as zero for future compatibility. 4 IOR: Enable IOR Mode (Instant Overload ...
Page 38
PLL Control Register Address: Attributes b[7] Description Default 0 Bit 7:2 Reserved. Write as zero for future compatibility. 1 SHBW: Set PLL to High Bandwidth. The selection of the PLL bandwidth permits to set the sensitivity of the PLL to ...
Page 39
LVDS Input Clock – Hysteresis Address: 0Ah Attributes Write Only. Register 0Bh reads back contents of register 0Ah. b[7] b[6] Description Reserved Default 0 0 Bit 7:6 Reserved. Write as zero for future compatibility. 5 INVCLK: Invert Input Reference Clock. ...
Page 40
Serializer Custom Pattern 0 Register Address: Attributes This register in conjunction with User Register 12 provides storage for the custom de-skew pattern. See User Register 16 for a description of how this training sequence is used. b[7] b[6] Description Default ...
Page 41
Decimator Clipping Control Register Address: 14h Attributes Write Only. Register 15h reads back contents of Register 14h. b[7] b[6] Description CGS Reserved Default 0 0 Bit 7 CGS: Custom Gain Setting. This bit is used to override the automatic gain ...
Page 42
Coefficent a[2:0] Coefficent b[2:0] 010 010 010 001 010 000 010 111 010 110 001 001 001 000 001 111 001 110 000 001 000 000 000 111 000 110 111 001 111 000 111 111 111 110 110 001 ...
Page 43
Decimator Control Register Address: 16h Attributes Write Only. Register 17h reads back contents of register 16h. b[7] b[6] Description Reserved Default 0 0 Bit 7:5 Reserved. Write as zero for future compatibility. 4 EQON: Equalizer Enable. This bit is used ...
Page 44
LVDS Control Register Address: Attributes b[7] b[6] Description Reserved Default 0 0 Bit 7:5 Reserved. Write as zero for future compatibility. 4 TX_term: Enable Internal 100 Ohm termination for data outputs 3:2 I_drive[1:0]: Controls the current drive of ...
Page 45
Chip ID Register Address: 1Eh Attributes Read Only. b[7] b[6] Description Default 0 0 Bit 7:0 ID[7:0]: Chip ID Register. Reading from this register will provide the chip version. The expected Chip ID for the ADC12EU050 is 12. ...
Page 46
Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 68-Lead LLP Package 10x10x1.0mm, 0.5mm Pitch Ordering Numbers ADC12EU050CIPLQ NS Package Number LQA68A 46 ...
Page 47
Notes 47 www.national.com ...
Page 48
... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...