adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 29

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

The recommended way to enable IOR mode is by setting bit
4 (IOR) of the Modulator Overload Control register (04h). Set-
ting this bit will enable IOR mode with the default settings for
DGF in the Decimator Clipping Control register (14h) and OL
in the Modulator Overload Control register (04h). Setting the
IOR mode bit to 0 will restore DGF and OL to their default
values, hence putting the chip back into ADC mode.
As can be seen in the Electrical Specifications, using IOR
mode gives a slight reduction in SNR performance, and also
a reduction of the full scale input range to 1.56Vpp differential.
Advanced Use of IOR Mode
The registers described above allow the user to customize
IOR mode. In order to correctly set the DGF and OL values,
it is necessary to understand how the IOR mode functions.
The implementation of IOR mode in the ADC consists of ana-
log and digital parts working in tandem.
The analog clipping circuitry, controlled by OL, is designed to
protect the sigma delta modulator from large signal inputs.
2.7 THE VOLTAGE REFERENCE
The ADC provides an on chip, ±5% tolerance voltage refer-
ence, together with all necessary biasing circuits and current
sources. A 10kΩ (±1%) resistor must be connected between
R
the ADC. The internal reference voltage, V
the R
REF
REF
and AGND in order to establish the biasing current of
pin.
FIGURE 20. IOR Mode Signal Modification
REF
, is available at
29
Using an analog clamp, signals are soft-limited to the less
than the 2.10Vpp full scale range of the modulator. OL gives
the value at which the circuit will begin to clamp.
The digital filter of the ADC12EU050 is where the full scale
input range is selected and the hard limiting of the signal takes
place. DGF selects the gain of the digital filter, and hence the
new full scale input range of the ADC.
In order to set a custom value for DGF, CGS, bit 7 of the Dec-
imator Clipping Control register, must be set. The DGF can
then be set, based on the application requirements.
OL should then be set to a value approximately half-way be-
tween the new full scale input range (which was just selected
by DGF) and the default full scale input range of 2.10Vpp. OL
must be set to a value higher than DGF, otherwise the signal
will be limited by the analog clipping circuitry, rather than the
digtal circuitry, and overload recovery will be impacted.
When using the internal reference, V
ed to AGND through a 100nF capacitor, while V
connected to AGND.
Chip-to-chip gain matching between several ADC12EU050
ADCs can be improved by connecting the V
ADCs. This is show in the figure below.
REFT
should be connect-
REFT
REFB
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pins of the
30051128
must be