adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 30

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
If a tighter tolerance reference is required for improved ther-
mal stability, an external voltage reference can be connected
between the V
connected even when using an external reference.
2.8 D
The D
between the DAC bias block and the DAC in the sigma-delta
modulator. The filter blocks noise from the DAC Bias block
from entering the DAC. Any noise which passes through this
filter will be seen in the spectrum as side skirts around the
carrier. The filter circuit, which is a first order RC filter, is
shown in the diagram below.
The D
leakage, minimum 100nF capacitor. If the application is es-
pecially sensitive to close to the carrier phase noise, then it is
recommended to increase D
For other applications where close to the carrier phase noise
is not important, the capacitor can be kept small in order to
reduce costs and minimise board space. The corner frequen-
cy of this filter is determined by the equation:
CAP
CAP
CAP
CAPACITOR SELECTION
pin provides the capacitance for the low pass filter
pin must be connected to AGND through a low
REFT
FIGURE 22. D
and V
REFB
CAP
pins. The R
CAP
, up to a maximum of 10µF.
RC Filter
REF
resistor must be
FIGURE 21. Reference Sharing
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2.9 BOARD LAYOUT CONSIDERATIONS
Proper grounding, layout and routing are essential to ensure
accurate conversion in any high speed ADC.
Maintaining separate analog and digital areas of the board is
recommended in order to achieve the specified performance.
This includes using a split ground plane, since the significant
digital portion of the chip can produce noise on the digital/IO
ground (DGND).
When designing the ADC12EU050 into a system, It is critical
that the exposed pad is connected to analog ground (AGND).
The exposed pad provides the analog ground connection for
the ADC12EU050, and so this connection is required for elec-
trical rather than thermal reasons.
It is recommended to decouple the power supplies using a
large capacitor (e.g. 47µF) for low frequency noise, and small
capacitors (e.g. 100nF) placed close to each supply pin.
Analog and digital supplies (V
the same supply, however in this case it is recommended that
the supplies are isolated from each other with a ferrite bead
or inductor. If the IO driver supply (V
also be taken from the same supply, with isolation as de-
scribed above.
The clock and data output traces, as well as the clock input
trace (when using a differential input clock), should be routed
as 100Ω impedance differential pairs. If not using the option
for 100Ω internal termination, then the clock and data output
trances should be terminated with a 100Ω resistor close to the
receiver.
If the system requires regulators to provide the ADC12EU050
1.2V operating voltage, National Semiconductor recom-
mends the LP3878SD-ADJ Low Noise “Ceramic Stable” Ad-
justable Regulator or the LP3879 Low Noise “Ceramic Stable”
Regulator. Datasheets for both parts are available from the
National Semiconductor website.
f = 1/(2
π
R
DCAP
C
DCAP
)
A
and V
30051122
D
DR
) may be provided from
) is 1.2V, then it may