adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 37

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

Modulator Overload Control Register
Address:
Attributes
Description
Default
7:5
3:0
Bit
4
b[7]
0
Reserved. Write as zero for future compatibility.
IOR: Enable IOR Mode (Instant Overload Recovery)
This bit can be used to quickly enable IOR mode with the default IOR settings for DGF (see register
14h) and OL.
0
1
OL[3:0]: The bits define the differential peak voltage (in V
when in IOR mode. In IOR mode the analog clipping is set to 1.746 V
clipping of the analog input signal is disabled.
Should it be decided to over-ride the default setting, it is important to follow the guidelines for setting
OL, as described in the Applications Information section.
Reserved
IOR Mode Disabled
IOR Mode Enabled
b[6]
0
04h
Write Only.
Register 05h reads back contents of register 04h.
0 (IOR Mode default)
b[5]
0
OL[3:0]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
b[4]
IOR
0
37
b[3]
0
Description
b[2]
0
PP
OL[3:0]
) at which the analog input signal is clipped
b[1]
Clipping Voltage
0
PP
1.746
1.694
1.586
1.534
1.480
1.426
1.374
2.172
2.120
2.066
2.012
1.960
1.906
1.852
1.800
1.64
V
. In the default ADC mode
PP
b[0]
0
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