pc8477b National Semiconductor Corporation, pc8477b Datasheet - Page 37

• Manufacturer Part Number: pc8477b
• Description: Advanced Floppy Disk Controller
• Manufacturer: National Semiconductor Corporation

5 0 Functional Description
power Because the internal circuitry is driven from the oscil-
lator clock it will also be disabled while the oscillator is off
Upon entering the power down state the RQM (Request
For Master) bit in the MSR will be cleared
There are two ways the part can recover from the power
down state and re-enable the oscillator and data separator
The part will power up after a software reset via the DOR or
DSR Since a software reset requires reinitialization of the
controller this method can be undesirable The part will also
power up after a read or write to either the Data Register or
Main Status Register This is the preferred method of power
up since all internal register values are retained It may take
a few milliseconds for the oscillator to stabilize and the mP
will be prevented from issuing commands during this time
through the normal Main Status Register protocol That is
the RQM bit in the MSR will be a 0 until the oscillator has
stabilized When the controller has completely stabilized
from power up the RQM bit in the MSR is set to 1 and the
controller can continue where it left off
There are two modes of low power in the floppy controller
manual low power and automatic low power Manual low
power is enabled by writing a 1 to bit D6 of the DSR The
chip will go into low power immediately This bit will be
cleared to 0 after the chip is brought out of low power Man-
ual low power can also be accessed via the Mode com-
mand The function of the manual low power mode is a
logical OR function between the DSR low power bit and the
Mode command manual low power bit setting When using
an external clock with the PC8477B you must wait at least
2 ms after low power mode is invoked before turning off the
external clock This will insure the PC8477B is powered
down correctly
Automatic low power mode will switch the controller into low
power 500 ms after it has entered the idle state (based on
the 500 kb s MFM data rate) Once the auto low power
mode is set it does not have to be set again and the con-
troller will automatically go into low power mode after it has
entered the idle state Automatic low power mode can only
be set with the Mode command Power up from automatic
low power is performed by the method described above
(Continued)
37
The Data Rate Select Digital Output and Configuration
Control Registers are unaffected by the power down mode
They will remain active It is up to the user to ensure that the
Motor and Drive Select signals are turned off
5 11 RESET OPERATION
The PC8477B floppy controller can be reset by hardware or
software Hardware reset is enacted by pulsing the RESET
input pin A hardware reset will set all of the user address-
able registers and internal registers to their default values
The Specify command values will be don’t cares so they
must be reinitialized The major default conditions are FIFO
disabled FIFO threshold
Drive Polling enabled
A software reset can be performed through the Digital Out-
put Register or Data Rate Select Register The DSR reset
bit is self-clearing while the DOR reset bit is not self-clear-
ing If the LOCK bit in the Lock command was set to a 1
previous to the software reset the FIFO THRESH and
PRETRK parameters in the Configure command will be re-
tained In addition the FWR FRD and BST parameters in
the Mode command will be retained if LOCK is set to 1 This
function eliminates the need for total reinitialization of the
controller after a software reset
After a hardware or software reset the Main Status Register
is immediately available for read access by the mP It will
return a 00 hex value until all the internal registers have
been updated and the data separator is stabilized When
the controller is ready to receive a command byte the MSR
will return a value of 80 hex (Request for Master bit is set)
The MSR is guaranteed to return the 80 hex value within
2 5 ms after a hardware or software reset All other user
addressable registers other than the Main Status Register
and Data Register (FIFO) can be accessed at any time
even while the part is in reset
e
0 Implied Seeks disabled and