pc8477b National Semiconductor Corporation, pc8477b Datasheet

pc8477b

Manufacturer Part Number

pc8477b

Description

Advanced Floppy Disk Controller

Manufacturer

National Semiconductor Corporation

Datasheet

1.PC8477B.pdf (54 pages)

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C 1995 National Semiconductor Corporation

Functional Block Diagram

PC8477B (SuperFDC

Advanced Floppy Disk Controller

General Description

The PC8477B CMOS advanced floppy disk controller is an

enhanced version of National’s DP8473 floppy controller

The PC8477B is software compatible with the DP8473 and

NEC mPD765 floppy disk controllers In addition it is pin and

software compatible with the Intel 82077AA floppy control-

ler The PC8477B a 24 MHz crystal a device chip select

and a resistor package are all that is needed for a complete

PC-AT

The PC8477B includes advanced features such as a

16 byte FIFO (Burst and Non-Burst modes) support of Per-

pendicular Recording Mode disk drives PS 2 diagnostic

registers for Model 30 and Models 50 60 80 standard

CMOS disk I O and additional commands to control these

new features The 16 byte FIFO will increase system per-

formance at higher data rates and with multi-tasking bus

structures This controller is designed to fit into all PC-AT

EISA and PS 2 designs as well as other advanced applica-

tions

Features

SuperFDC

TRI-STATE is a registered trademark of National Semiconductor Corporation

IBM

Pin and software compatible with Intel 82077AA FDC

Software compatible with NSC’s DP8473

PC-AT and PS 2 are registered trademarks of International Business Machines Corp

is a trademark of National Semiconductor Corporation

PS 2 or EISA floppy controller solution

TL F 11332

)

FIGURE 1-1

16 byte FIFO (default disabled)

Perpendicular Mode Recording drive support

High performance internal analog data separator (no

external filter components required)

Low power CMOS with manual power down mode

Automatic power down mode for complete software

transparency

Integrates all PC-AT and PS 2 logic

Data Rate Support 250 300 kb s 500 kb s

and 1 Mb s

Write precompensation software programmable

68 pin PLCC package

60 pin PQFP package

Ideal for space limited applications

Burst and Non-Burst modes

Programmable threshold

On chip Oscillator

PC compatible FDC address decode

PS 2 Model 30 and Model 50 60 80 diagnostic

registers

DMA control circuitry

High current CMOS disk interface outputs

Data Rate and Digital Output registers

12 mA mP bus interface buffers

RRD-B30M75 Printed in U S A

August 1993

TL F 11332 – 3

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