pc8477b National Semiconductor Corporation, pc8477b Datasheet - Page 13

• Manufacturer Part Number: pc8477b
• Description: Advanced Floppy Disk Controller
• Manufacturer: National Semiconductor Corporation

3 0 Register Description
3 8 1 DIR PC-AT Mode
D7
D6 – D0
3 8 2 DIR PS 2 Mode
D7
D6 – D3
D2 – D1
D0
3 8 3 DIR Model 30 Mode
D7
D6 – D4
D3
D2
D1 – D0
3 9 CONFIGURATION CONTROL REGISTER (CCR) Write
Only
This is the write only data rate register commonly used in
PC-AT applications This register is not affected by a soft-
ware reset and is set to 250 kb s after a hardware reset
The data rate of the floppy controller is determined by the
last write to either the CCR or DSR
RESET
RESET
COND
COND
RESET
DESC DSKCHG 0
DESC DSKCHG
COND
DESC
DSKCHG
N A
N A
D7
D7
N A
Disk Changed Active high status of DSKCHG
disk interface input independent of INVERT
value
Undefined TRI-STATE Used by hard disk con-
troller status register
Disk Changed Active high status of DSKCHG
disk interface input independent of INVERT
value
Reserved Always 1
Data Rate Select 1 0 These bits indicate the
status of the DRATE1 – 0 bits programmed
through the DSR CCR
High Density This bit is low when the 1 Mb s
or 500 kb s data rate is chosen and high when
the 300 kb s or 250 kb s data rate is chosen
This bit is independent of the IDENT or INVERT
value
Disk Changed Active low status of DSKCHG
disk interface input independent of INVERT
value
Reserved Always 0
DMA Enable Active high status of the DMAEN
bit in the DOR
No Precompensation Active high status of the
NOPRE bit in the CCR
Data Rate Select 1 0 These bits indicate the
status of the DRATE1 – 0 bits programmed
through the DSR CCR
D7
D6 D5 D4
N A N A N A N A
0
D6
1
N A
D6
X
0
0
D5
1
0 DMAEN NOPRE DRATE1 DRATE0
0
N A
D5
X
D4
1
D3
0
N A
D4
D3
X
1
DRATE1 DRATE0
N A
D2
D3
0
X
N A
D2
(Continued)
N A
D2
X
D1
1
N A
D1
N A
D1
X
D0
HIGH
DEN
0
N A
D0
D0
X
1
13
3 9 1 CCR PC-AT and PS 2 Modes
D7 – D2
D1 – D0
3 9 2 CCR Model 30 Mode
D7 – D3
D2
D1 – D0
3 10 RESULT PHASE STATUS REGISTERS
The Result Phase of a command contains bytes that hold
status information The format of these bytes are described
below Do not confuse these status bytes with the Main
Status Register which is a read only register that is always
valid The Result Phase status registers are read from the
Data Register (FIFO) only during the Result Phase of certain
commands (see Section 4 1 Command Set Summary) The
status of each register bit is indicated when the bit is a 1
3 10 1 Status Register 0 (ST0)
D7 – D6
D5
D4
D3
RESET
RESET
COND
COND
DESC
DESC
RESET
COND
DESC
N A N A N A N A N A
N A N A N A N A N A N A
D7 D6 D5 D4 D3
D7
0
0
D7
IC
Reserved Should be set to 0
Data Rate Select 1 0 These bits determine the
data rate of the floppy controller See Table 3-6
for the appropriate values
Reserved Should be set to 0
No Precompensation This bit can be set by
software but it has no functionality It can be
read by bit D2 of the DIR when in the Model 30
register mode Unaffected by a software reset
Data Rate Select 1 0 These bits determine the
data rate of the floppy controller See Table 3-6
for the appropriate values
Interrupt Code
00
01
10
11
Seek End Seek Relative Seek or Recalibrate
command completed by the controller (Used
during a Sense Interrupt command )
Equipment Check After a Recalibrate com-
mand Track 0 signal failed to occur (Used dur-
ing Sense Interrupt command )
Not Used Always 0
0
0
D6
e
e
e
e
0
D6
IC
0
Normal Termination of Command
Abnormal Termination of Command Exe-
cution of command was started but was
not successfully completed
Invalid Command Issued Command is-
sued was not recognized as a valid com-
mand
Internal drive ready status changed state
during the drive polling mode Only occurs
after a hardware or software reset
0
D5
0
D5
SE
0
0
D4
0
D4
EC
0
0 NOPRE DRATE1 DRATE0
D3
0
D3
0
0
D2
D2
0
0
HDS
D2
DRATE1 DRATE0
0
D1
D1
1
1
DS1
D1
0
D0
D0
DS0
0
0
D0
0