s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 137

• Manufacturer Part Number: s908ab32ag0cfue
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908AB32
Freescale Semiconductor
—
Rev. 1.1
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode is used also to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. See
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL start-up, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. See
Circuit. If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See
The following conditions apply when the PLL is in automatic bandwidth
control mode:
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below f
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9.7 Interrupts
The ACQ bit (see
(PBWC)) is a read-only indicator of the mode of the filter. (See
9.4.2.2 Acquisition and Tracking
The ACQ bit is set when the VCO frequency is within a certain
tolerance ∆
certain tolerance ∆
Specifications)
The LOCK bit is a read-only indicator of the locked state of the
PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance ∆
a certain tolerance ∆
Specifications)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See
Control Register
Clock Generator Module (CGM)
9.6.2 PLL Bandwidth Control Register
TRK
LOCK
for information and precautions on using interrupts).
and is cleared when the VCO frequency is out of a
and is cleared when the VCO frequency is out of
9.6.2 PLL Bandwidth Control Register
(PCTL))
UNT
UNL
. (See
. (See
9.10 Acquisition/Lock Time
9.10 Acquisition/Lock Time
Modes)
9.4.3 Base Clock Selector
Clock Generator Module (CGM)
(PBWC). If PLL
9.6.1 PLL
Technical Data
BUSMAX
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