s908ab32ag0cfue Freescale Semiconductor, Inc, s908ab32ag0cfue Datasheet - Page 136

no-image

s908ab32ag0cfue

Manufacturer Part Number
s908ab32ag0cfue
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
s908ab32ag0cfueR
Manufacturer:
FREESCALE
Quantity:
20 000
Clock Generator Module (CGM)
9.4.2.2 Acquisition and Tracking Modes
9.4.2.3 Manual and Automatic PLL Bandwidth Modes
Technical Data
136
then slightly alters the DC voltage on the external capacitor connected
to CGMXFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency f
condition based on this comparison.
The PLL filter is manually or automatically configurable into one of two
operating modes:
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
Acquisition mode — in acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL start-
up or when the PLL has suffered a severe noise hit and the
resulting VCO frequency is much different from the desired
frequency. When in acquisition mode, the ACQ bit is clear in the
PLL bandwidth control register. See
Control Register
Tracking mode — in tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. See
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
Clock Generator Module (CGM)
RDV
9.4.2.2 Acquisition and Tracking
. The circuit determines the mode of the PLL and the lock
9.4.3 Base Clock Selector
(PBWC).
9.6.2 PLL Bandwidth
MC68HC908AB32
Modes. The value of the
Circuit. The PLL is
Freescale Semiconductor
Rev. 1.1

Related parts for s908ab32ag0cfue