SSTUG32868 NXP Semiconductors, SSTUG32868 Datasheet - Page 14

• Manufacturer Part Number: SSTUG32868
• Description: Sstug32868 1.8 V 28-bit 1 2 Configurable Registered Buffer With Parity For Ddr2-1g Rdimm Applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SSTUG32868_1
Product data sheet
Fig 7. Timing diagram during normal operation (RESET = HIGH)
Dn, DODTn,
Qn, QODTn,
(1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked in at m + 1, the QERR output signal will be generated
QERR
CSGEN
PAR_IN
RESET
DCKEn
QCKEn
DCSn
on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. If an error occurs and the QERR output is driven LOW,
it stays LOW for a minimum of two clock cycles or until RESET is driven LOW.
CK
CK
(1)
unknown input event
t
PDM
, t
CK to Q
PDMSS
t
su
m
t
output signal is dependent
on the prior unknown event
h
Rev. 01 — 23 April 2007
1.8 V DDR2-1G configurable registered buffer with parity
t
data to QERR latency
su
m
t
h
1
m
2
HIGH or LOW
m
SSTUG32868
3
CK to QERR
t
PHL
, t
© NXP B.V. 2007. All rights reserved.
PLH
m
4
002aab900
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