SSTUA32S869BHLF IDT, Integrated Device Technology Inc, SSTUA32S869BHLF Datasheet
SSTUA32S869BHLF
Specifications of SSTUA32S869BHLF
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SSTUA32S869BHLF Summary of contents
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Integrated Circuit Systems, Inc. 14-Bit Configurable Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533 and 667 Product Features: • 14-bit 1:2 registered buffer with ...
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Ball Assignments VDD (1) MCL B VDD NB VDD C QCKEA VDD NB D Q2A VDD GND E Q3A VDD NB F QODTA VDD GND G Q5A VDD GND H Q6A NB GND J QCSA# ...
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Parity and Standby Function Table RESET# DCS# CSR ...
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General Description The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All ...
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Terminal Functions Signal Group Signal Name Ungated inputs DCKE, DODT Chip Select (1) D1 ... D14 gated inputs Chip Select DC inputs Re-driven Q1A...Q14A, outputs Q1B ... Q14B, QCSA#, QCSB# QCKEA,QCKEB QODTA,QODTB Parity input PARIN1 Parity output PPO1 Parity error ...
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Block Diagram VREF PARIN1 D1 D14 DCS# CSR# DCKE DODT RESET# CK CK# 1173—10/28/05 Advance Information LSP0 internal node (CS Active) PARITY GENERATOR AND CHECKER ...
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Block Diagram RESET# CLK CLK D3 D6 D14 V REF PAR_IN 1, 2 PAR_IN 2 C1, C2 NOTE 2 PARIN 1 is used to generate PPO1 and PTYERR1#. 1173—10/28/05 LPSO (Internal Node) D ...
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Register Timing RESET# DCS# CSR# CLK CLK# ( D14 ( Q14 (2) PAR_IN1, PAR_IN2, PPO1, (2) PPO2 (2) PTYERR1#, PTYERR2#, Note 1 This range doesn't include D1, D4 and D7 and their corresponding outputs 1173—10/28/05 n ...
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Register Timing RESET# DCS# CSR# CLK CLK Q14 (2) PAR_IN1, PAR_IN2 (2) PPO1, PPO2 (not used) PTYERR1#, (2) PTYERR2# Note 1: This range doesn't include D1, D4 and D7 and their corresponding outputs ...
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Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...
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Electrical Characteristics - 70° 2.5 +/-0.2V DDQ SYMBOL PARAMETERS -18mA All Inputs ...
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Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS f Clock frequency clock t Differential inputs active time ACT t Differential inputs inactive time INACT t Setup time S Hold time t H Hold time 1 ...
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CK Inputs Test Point R = 100Ω L Test Point LVCMOS RESET Inp act I DD (see 10% Note 2) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES t w Inpu t V ...
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Output slew rate measurement information (V All input pulses are supplied by generators having the following characteristics: PRR 10 MHz input slew rate = 1 V/ns ± 20%, unless otherwise specified. o (1) C includes probe ...
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Error output load circuit and voltage measurement information (V All input pulses are supplied by generators having the following characteristics: PRR 10 MHz input slew rate = 1 V/ns ± 20%, unless otherwise specified. o (1) ...
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C includes probe and jig capacitance Output Cross Point Voltage ICR V = 600mV i(P-P) t and t are the same PLH PHL PD Figure 23 ...
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E ALL DIMENSIO NS IN MILLIMETERS Min/Max 13. 8.00 Bsc 0.90/1.20 0.65 Bsc Note: B all grid total indic ates max imum ball count for pack age. Les ser quantity may be used. Ordering Information ...
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Revision History Rev. Issue Date Description 0.1 10/27/2005 Initial Release. 1173—10/28/05 ICSSSTUA32S869B Advance Information 18 Page # - ...