74SSTUA32866BFG8 IDT, Integrated Device Technology Inc, 74SSTUA32866BFG8 Datasheet
74SSTUA32866BFG8
Specifications of 74SSTUA32866BFG8
Related parts for 74SSTUA32866BFG8
74SSTUA32866BFG8 Summary of contents
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES: • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer • Control inputs compatible with LVCMOS levels ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTIONAL BLOCK DIAGRAM (1: CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS (D3, D5, D6, D8-D14) COMMERCIAL TEMPERATURE RANGE 1D C1 ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTIONAL BLOCK DIAGRAM (1: CONFIGURATION (POSITIVE LOGIC) RESET CLK CLK V REF DCKE DODT DCS CSR OTHER CHANNELS (D2-D6, D8-D10, D12-D13) COMMERCIAL TEMPERATURE RANGE ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST PIN CONFIGURATION (TYPE A) 6 Q2B Q3B QCKEB QODTB 5 QCKEA Q2A Q3A QODTA 4 V GND V GND GND V GND DD REF 2 PPO DNU DNU ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTIONAL BLOCK DIAGRAM (1:1) RESET CLK1 CLK1 V REF DCKE DODT DCS CSR OTHER CHANNELS (D3, D5, D6, D8-D25) COMMERCIAL TEMPERATURE RANGE ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST PIN CONFIGURATION DNU 6 Q15 Q16 DNU 5 QCKE Q2 Q3 QODT 4 V GND V GND GND V GND DD REF 2 PPO D15 D16 QERR 1 ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FUNCTION TABLE (EACH FLIP-FLOP) (1) RESET DCS CSR ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST LOGIC DIAGRAM (1:1) G2 RESET H1 CLK J1 CLK (Internal Node D3 D6 D25 A3 REF PAR_IN G6 C0 Counter ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST LOGIC DIAGRAM (1:2) G2 RESET H1 CLK J1 CLK (Internal Node D3 D6 D14 D A3 REF PAR_IN G6 ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply Voltage Range DD (2,3) V Input Voltage Range I (2,3) V Output Voltage Range O I Input Clamp Current V < ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST OPERATING CHARACTERISTICS, T Symbol Parameter V Supply Voltage DD V Reference Voltage REF V Termination Voltage TT V Input Voltage High-Level Input Voltage Low-Level Input Voltage ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE Symbol Parameter f Clock Frequency CLOCK tw Pulse Duration, CLK, CLK HIGH or LOW ACT (1,2) t Differential Inputs Active Time INACT (1,3) t ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST REGISTER TIMING RESET DCS CSR CLK CLK D1 - D25 Q1 - Q25 PAR_IN PPO QERR Timing Diagram for SSTUA32866 Used as a Single Device ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST REGISTER TIMING RESET DCS CSR CLK CLK D1 - D14 Q1 - Q14 PAR_IN PPO QERR (not used) Timing Diagram for the First SSTUA32866 (1:2 Register-A Configuration) Device Used in a Pair; ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST REGISTER TIMING RESET DCS CSR CLK CLK D1 - D14 Q1 - Q14 (1) PAR_IN PPO (not used) QERR Timing Diagram for the First SSTUA32866 (1:2 Register-B Configuration) Device Used in a ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TEST CIRCUITS AND WAVEFORMS (V CLK Inputs LVCMOS RESET Input t INACT I DD 10% Voltage and Current Waveforms Inputs Active and Inactive Times t W Input V ICR ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TEST CIRCUITS AND WAVEFORMS (V Output Output NOTES includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST TEST CIRCUITS AND WAVEFORMS (V DUT Out Load Circuit: QERR QERR QERR Output QERR QERR DUT Out Load Circuit: Partial-Parity-Out Load Circuit ...
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IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST ORDERING INFORMATION XX XXX IDT SSTUA32 Temp. Range Device Type XX Package BFG Low Profile, Fine Pitch, Ball Grid Array - Green 866 1.8V Configurable Registered Buffer with Address-Parity Test 74 0°C ...