isl6363 Intersil Corporation, isl6363 Datasheet - Page 29

• Manufacturer Part Number: isl6363
• Description: Multiphase Pwm Regulator For Vr12™ Desktop Cpus
• Manufacturer: Intersil Corporation

NTC Network on the NTC and the NTCG pins
The controller drives 60µA current source out of the NTC pin and
the NTCG pin alternatively at 1kHz frequency with 50% duty
cycle. The current source flows through the respective NTC
resistor networks on the pins and creates voltages that are
monitored by the controller through an A/D converter to generate
the TZONE value. Table 10 shows the programming table for
TZONE. The user needs to scale the NTC (and NTCG) network
resistance such that it generates the NTC (and NTCG) pin voltage
that corresponds to the left-most column. Do not use any
capacitor to filter the voltage. On ADC Output = 7, the controller
issues thermal alert to the CPU, on ADC Output <7, the controller
asserts the VR_HOT# signal.
Current Monitor
Refer to Equation 18 for the IMON pin current expression.
Referencing the “Simplified Application Circuit” on page 6, the
IMON pin current flows through R
expressed in Equation 39:
Rewriting Equation 38 gives Equation 40:
Substitution of Equation 40 into Equation 39 gives Equation 41:
Rewriting Equation 41 and application of full load condition gives
Equation 42:
V
I
V
R
droop
Rimon
Rimon
imon
VNTC (V)
0.64
0.68
0.72
0.76
0.80
0.84
0.88
0.92
0.96
1.00
1.04
1.08
1.12
1.16
>1.2
1.2
=
=
=
=
----------------- -
R
V
--------------------------------------------
3
3I
-------------------- -
droop
Rimon
R
I
×
o
droop
o
3I
TABLE 10. TZONE PROGRAMMING TABLE
I
×
droop
o
LL
×
×
×
LL
×
R
ADC OUTPUT
LL
droop
×
R
imon
R
imon
D
0
1
2
3
4
5
6
7
8
9
A
B
C
E
F
29
imon
. The voltage across R
%TMAX
>100%
>100%
>100%
>100%
>100%
>100%
100%
<76%
97%
94%
91%
88%
85%
82%
79%
76%
TZONE
07h
03h
01h
01h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
7Fh
3Fh
1Fh
0Fh
(EQ. 39)
(EQ. 40)
(EQ. 41)
(EQ. 42)
imon
ISL6363
is
For example, given LL = 1.9mΩ, R
V
R
A capacitor C
pin voltage. The R
is recommended to have a time constant long enough such that
switching frequency ripples are removed.
Current Balancing
The ISL6363 achieves current balancing through matching the
ISEN pin voltages. R
switching ripple of the phase node voltages. It is recommended
to use a rather long R
voltages have minimal ripple and represent the DC current
flowing through the inductors. Recommended values are
R
Optional Slew Rate Compensation Circuit for
1-Tick VID Transition
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate. For example, the DAC may change a tick
(5mV) per 0.5µs, controlling output voltage V
10mV/µs.
Rimon
imon
s
FIGURE 27. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR
= 10kΩ and C
= 25.2kΩ.
= 2.7V at I
COMP
Idroop_vid
VID<0:6>
imon
1-TICK VID TRANSITION
Vcore
INTERNAL
Vfb
s
Ivid
imon
omax
can be paralleled with R
TO IC
= 0.22µF.
E/A
isen
isen
C
imon
= 53A, Equation 42 gives
and C
C
FB
isen
Σ
time constant is the user’s choice. It
Idroop_vid
isen
VDAC
time constant such that the ISEN
Rvid Cvid
Rdroop
droop
form filters to remove the
Ivid
DAC
X 1
= 2.825kΩ,
imon
VIDs
RTN
VSS
CORE
to filter the IMON
OPTIONAL
September 29, 2011
VID<0:6>
VSSSENSE
Vcore
slew rate at
FN6898.0