isl6363 Intersil Corporation, isl6363 Datasheet - Page 11

• Manufacturer Part Number: isl6363
• Description: Multiphase Pwm Regulator For Vr12™ Desktop Cpus
• Manufacturer: Intersil Corporation

Gate Driver Timing Diagram
Theory of Operation
Multiphase R3 Modulator
The ISL6363 is a multiphase regulator implementing Intel’s™
VR12™ protocol. It has two voltage regulators, VR1 and VR2, on
one chip. VR1 can be programmed for 1, 2, 3, or 4-phase
operation, and VR2 is dedicated for 1-phase operation. The
following description is based on VR1, but also applies to VR2
because the same architecture is implemented.
The ISL6363 uses Intersil’s patented R3 (Robust Ripple Regulator)
modulator. The R3 modulator combines the best features of fixed
frequency PWM and hysteretic PWM while eliminating many of
their shortcomings. Figure 3 conceptually shows the multiphase
R3 modulator circuit, and Figure 4 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C
g
waveform traversing between the VW and COMP voltages. It resets
to VW when it hits COMP, and generates a one-shot master clock
signal. A phase sequencer distributes the master clock signal to
the slave circuits. If VR1 is in 4-phase mode, the master clock
signal will be distributed to the four phases, and the Clock1~4
signals will be 90° out-of-phase. If VR1 is in 3-phase mode, the
master clock signal will be distributed to the three phases, and the
Clock1~3 signals will be 120° out-of-phase. If VR1 is in 2-phase
mode, the master clock signal will be distributed to Phases 1 and 2,
and the Clock1 and Clock2 signals will be 180° out-of-phase. If
VR1 is in 1-phase mode, the master clock signal will be distributed
to Phase 1 only and be the Clock1 signal.
m
V
o
, where g
m
UGATE
LGATE
is a gain factor. C
PWM
t
FL
11
rm
rm
t
1V
with a current source equal to
LGFUGR
voltage V
crm
t
RU
is a sawtooth
ISL6363
1V
t
UGFLGR
t
FU
Each slave circuit has its own ripple capacitor C
mimics the inductor ripple current. A g
inductor voltage into a current source to charge and discharge
C
clock signal, and the current source charges C
voltage V
and the current source discharges C
rs
. The slave circuit turns on its PWM pulse upon receiving the
Crs1
Crs2
Crs3
gmVo
MASTER
t
CLOCK
RL
Crs
Vcrs1
Vcrs2
Vcrs3
hits VW, the slave circuit turns off the PWM pulse,
VW
VW
VW
VW
FIGURE 3. R3 MODULATOR CIRCUIT
Vcrm
COMP
Crm
MASTER CLOCK CIRCUIT
Clock3
Clock2
Clock1
gm
gm
gm
SLAVE CIRCUIT 1
SLAVE CIRCUIT 2
SLAVE CIRCUIT 3
MASTER
CLOCK
S
R
S
R
S
R
Q
Q
Q
PWM1
PWM2
PWM3
Sequencer
rs
Phase
.
m
Phase1
Phase2
Phase3
amplifier converts the
rs
Clock1
Clock2
Clock3
rs
. When C
L1
I
L2
I
L3
I
, whose voltage
September 29, 2011
L1
L2
L3
Vo
rs
FN6898.0
Co