isl6363 Intersil Corporation, isl6363 Datasheet - Page 23

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isl6363

Manufacturer Part Number
isl6363
Description
Multiphase Pwm Regulator For Vr12™ Desktop Cpus
Manufacturer
Intersil Corporation
Datasheet

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Part Number:
isl6363CRTZ
Manufacturer:
INTERSIL
Quantity:
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current-sensing summing network. It is recommended to use
1Ω~10Ω R
smaller than the rest of the current sensing circuit, the following
analysis will ignore it for simplicity.
The summed inductor current information is presented to the
capacitor C
frequency-domain relationship between inductor total current
I
Where N is the number of phases.
Transfer function A
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC R
values decreases as its temperature decreases. Proper
selections of R
V
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC network
and the R
fraction of the inductor DCR voltage. It is recommended to have a
higher ratio of V
has higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R
R
need to be fine tuned on actual boards. One can apply full load DC
current and record the output voltage reading immediately; then
record the output voltage reading again when the board has
reached the thermal steady state. A good NTC network can limit the
output voltage drift to within 2mV. It is recommended to follow the
Intersil evaluation board layout and current-sensing network
parameters to minimize engineering time.
V
achieve good transient response. Transfer function A
pole w
V
R
ω
A
ω
o
Cn
Cn
Cn
ntc
ntcnet
(s) and C
cs
sns
L
(s) also needs to represent real-time I
s ( )
s ( )
=
represent the inductor total DC current over the temperature
= 10kΩ (ERT-J1VR103J). The NTC network parameters may
=
DCR
----------- -
sns
=
=
L
------------------------------------------------------
---------------------------------------- -
R
R
=
sum
ntcnet
ntcnet
----------------------
1
and a zero w
n
(
-------------------------------------------------- -
---------------------------------------- -
R
1
o
n
+
R
R
ntcnet
voltage V
to create quality signals. Since R
. Equations 19 thru 23 describe the
+
ntcs
ntcs
----------- -
ω
resistors form a voltage divider, V
------
ω
R
sns
sum
s
s
cn
L
×
+
ntcnet
1
+
+
R
------------- -
R
------------- -
to the inductor DCR voltage, so the droop circuit
+
, R
R
R
sum
sum
cs
N
N
sum
R
------------- -
ntc
ntc
(s) always has unity gain at DC. The inductor
Cn
sum
ntcs
N
L
)
×
+
(s):
. One needs to match w
= 3.65kΩ, R
×
C
R
, R
×
R
n
p
p
DCR
----------- -
p
N
and R
23
×
I
ntc
o
p
s ( )
= 11kΩ, R
parameters ensure that
×
o
A
(s) for the controller to
cs
o
s ( )
value is much
cn
ntcs
L
is always a
and w
= 2.61kΩ and
cs
(s) has a
sns
(EQ. 19)
(EQ. 20)
(EQ. 22)
(EQ. 23)
(EQ. 21)
ntc
so
ISL6363
A
and solving for the solution, Equation 24 gives Cn value.
For example, given N = 3, R
R
Equation 24 gives C
Assuming the compensator design is correct, Figure 17 shows the
expected load transient response waveforms if C
selected. When the load current I
output voltage V
If C
represent real-time I
Figure 18 shows the load transient response when C
small. V
create a system failure. Figure 19 shows the transient response
when C
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
C
FIGURE 18. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN C
cs
ntcs
FIGURE 17. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
n
n
(s) is unity gain at all frequencies. By forcing w
=
value is too large or too small, V
= 2.61kΩ, R
----------------------------------------------------------- -
R
---------------------------------------- -
R
n
ntcnet
ntcnet
CORE
is too large. V
will sag excessively upon load insertion and may
×
+
R
------------- -
R
------------- -
CORE
L
sum
sum
N
N
ntc
n
o
= 10kΩ, DCR = 0.88mΩ and L = 0.36µH,
×
= 0.406µF.
also has a square response.
(s) and will worsen the transient response.
CORE
DCR
sum
is sluggish in drooping to its final
I
O I
V O
= 3.65kΩ, R
V O
I
V O
O
core
O
has a square change, the
Cn
(s) will not accurately
p
= 11kΩ,
n
n
September 29, 2011
n
is correctly
L
IS TOO SMALL
IS TOO LARGE
equal to w
n
is too
(EQ. 24)
FN6898.0
sns

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