isl6363 Intersil Corporation, isl6363 Datasheet - Page 17

• Manufacturer Part Number: isl6363
• Description: Multiphase Pwm Regulator For Vr12™ Desktop Cpus
• Manufacturer: Intersil Corporation

I
shown in Equation 2.
V
Changing R
slope. Since I
recommended to first scale I
then select an appropriate R
load line slope.
Differential Voltage Sensing
Figure 9 also shows the differential voltage sensing scheme.
VCC
from the processor die. A unity gain differential amplifier senses
the VSS
amplifier regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 3:
Rewriting Equation 3 and substitution of Equation 2 gives
Equation 4 is the exact equation required for load line
implementation.
The VCC
The feedback will be open circuit in the absence of the processor. As
Figure 9 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
The ISL6363 monitors individual phase average current by
monitoring the ISEN1, ISEN2, ISEN3, and ISEN4 voltages.
Figure 10 shows the current balancing circuit recommended for
ISL6363 for a 3-Phase configuration as an example. Each phase
node voltage is averaged by a low-pass filter consisting of R
and C
should be routed to the inductor phase-node pad in order to
VCC
VCC
V
droop
droop
droop
FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE
SENSE
COMP
SENSE
SENSE
isen
flows through resistor R
is the droop voltage required to implement load line.
SENSE
=
SENSE
, and presented to the corresponding ISEN pin. R
R
and VSS
+
–
INTERNAL
droop
droop
VSS
V
TO IC
droop
droop
IMPLEMENTATION
voltage and add it to the DAC output. The error
and VSS
E/A
SENSE
×
or scaling I
SENSE
I
also sets the overcurrent protection level, it is
droop
=
FB
V
SENSE
Σ
=
DAC
are the remote voltage sensing signals
V
Idroop
VDAC
DAC
+
droop
droop
signals come from the processor die.
droop
VSS
Rdroop
Vdroop
droop
17
–
DAC
X 1
R
SENSE
droop
can both change the load line
value to obtain the desired
based on OCP requirement,
VID
and creates a voltage drop as
×
RTN
VSS
I
droop
RESISTOR
“CATCH”
RESISTOR
“CATCH”
VCC
VSS
VR LOCAL VO
SENSE
SENSE
isen
(EQ. 2)
(EQ. 3)
(EQ. 4)
ISL6363
isen
eliminate the effect of phase node parasitic PCB DCR.
Equations 5 through 7 give the ISEN pin voltages:
Where R
and R
side pad and the output voltage rail; and I
inductor average currents.
The ISL6363 will adjust the phase pulse-width relative to the
other phases to make V
I
R
Using the same components for L1, L2 and L3 will provide a good
match of R
R
layout for the power delivery path between each inductor and the
output voltage rail, such that R
FIGURE 11. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
Sometimes it is difficult to implement symmetrical layout. For
the circuit shown in Figure 10, asymmetric layout causes
different R
Figure 11 shows a differential-sensing current balancing circuit
recommended for the ISL6363. The current sensing traces
should be routed to the inductor pads so they only pick up the
inductor DCR voltage. Each ISEN pin sees the average voltage of
V
V
V
L1
ISEN1
ISEN2
ISEN3
pcb1
pcb1
INTERNAL
= I
INTERNAL
TO IC
pcb3
L2
, R
TO IC
= R
ISEN3
ISEN2
ISEN1
=
=
=
dcr1
pcb2
= I
ISEN3
ISEN2
ISEN1
pcb2
Cisen
Cisen
(
(
(
Cisen
pcb1
R
R
R
are parasitic PCB DCR between the inductor output
dcr1
L3
FIGURE 10. CURRENT BALANCING CIRCUIT
dcr1
dcr2
dcr3
, R
and R
, when there are R
= R
, R
, R
dcr2
Phase3
+
+
+
Phase1
Phase3
Phase2
dcr2
Phase1
pcb2
Phase2
R
R
R
pcb3
pcb3
pcb1
pcb2
pcb3
and R
Cisen
Cisen
Cisen
Risen
Risen
Risen
Risen
Risen
Risen
Risen
Risen
Risen
Risen
Risen
Risen
and R
.
and R
ISEN1
. It is recommended to have symmetrical
)
)
)
V1p
V2p
×
×
×
dcr3
V3p
I
I
I
L1
L2
L3
dcr3
pcb3
= V
are inductor DCR; R
pcb1
dcr1
. Board layout will determine
ISEN2
, thus current imbalance.
L3
L2
L1
= R
= R
L1
L2
L3
IL3
IL2
IL1
= V
pcb2
dcr2
Rdcr3
Rdcr2
Rdcr1
IL3
IL2
IL1
L1
Rdcr1
ISEN3
Rdcr2
Rdcr3
, I
= R
= R
L2
V3n
V2n
V1n
Rpcb3
Rpcb2
Rpcb1
, thus, to achieve
pcb3
dcr3
and I
September 29, 2011
Rpcb2
Rpcb1
pcb1
Rpcb3
.
and
L3
, R
are
V o
FN6898.0
pcb2
V o
(EQ. 5)
(EQ. 6)
(EQ. 7)