isl6363 Intersil Corporation, isl6363 Datasheet - Page 22

• Manufacturer Part Number: isl6363
• Description: Multiphase Pwm Regulator For Vr12™ Desktop Cpus
• Manufacturer: Intersil Corporation

06h
10h
11h
12h
1Ch
21h
22h
24h
25h
26h
30h
INDEX
TABLE 6. SUPPORTED DATA AND CONFIGURATION
Capability
Status_1
Status_2
Temperature
Zone
Status_2_
LastRead
ICC max
Temp max
SR-fast
SR-slow
V
Vout max
BOOT
REGISTER
NAME
REGISTERS (Continued)
Identifies the SVID VR
capabilities and which of the
optional telemetry registers are
supported.
Data register read after ALERT#
signal. Indicating if a VR rail has
settled, has reached VRHOT
condition or has reached ICC
max.
Data register showing status_2
communication.
Data register showing
temperature zones that have
been entered.
This register contains a copy of
the Status_2 data that was last
read with the GetReg (Status_2)
command.
Data register containing the ICC
max the platform supports, set
at start-up by resistors Rprog1
and Rprog2. The platform
design engineer programs this
value during the design process.
Binary format in amps, i.e.,
100A = 64h
Data register containing the
temperature max the platform
support, set at startup by
resistor Rprog2. The platform
design engineer programs this
value during the design process.
Binary format in °C, i.e.,
+100°C = 64h
Slew Rate Normal. The fastest
slew rate the platform VR can
sustain. Binary format in
mV/µs. i.e., 0Ah = 10mV/µs.
Is 4x slower than normal. Binary
format in mV/µs. i.e.,
02h = 2.5mV/µs
If programmed by the platform,
the VR supports V
during start-up ramp. The VR will
ramp to V
V
SetVID command to move to a
different voltage.
This register is programmed by
the master and sets the
maximum VID the VR will
support. If a higher VID code is
received, the VR will respond
with “not supported”
acknowledge.
BOOT
until it receives a new
22
DESCRIPTION
BOOT
and hold at
BOOT
voltage
81h
00h
00h
00h
00h
Refer to
Table 7
Refer to
Table 8
0Ah
02h
00h
FBh
DEFAULT
VALUE
ISL6363
Key Component Selection
Inductor DCR Current-Sensing Network
Figure 16 shows the inductor DCR current-sensing network for a
3-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in R
and R
current by sensing the DCR voltage drop. The R
resistors are connected in a summing network as shown, and feed
the total current information to the NTC network (consisting of
R
temperature coefficient (NTC) thermistor, used to
temperature-compensate the inductor DCR change.
The inductor output side pads are electrically shorted in the
schematic, but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
31h
32h
33h
34h
INDEX
ntcs
TABLE 6. SUPPORTED DATA AND CONFIGURATION
DCR
, R
o
Phase1
L
connected to the pads to accurately sense the inductor
ntc
VID Setting
Power State
Voltage Offset Sets offset in VID steps added to
Multi VR Config Data register that configures
FIGURE 16. DCR CURRENT-SENSING NETWORK
REGISTER
and R
DCR
NAME
REGISTERS (Continued)
Phase2
L
Io
p
) and capacitor C
DCR
Phase3
L
Data register containing
currently programmed VID
voltage. VID data format.
Register containing the current
programmed power state.
the VID setting for voltage
margining. Bit 7 is a sign bit,
0 = positive margin,
1 = negative margin. Remaining
7 bits are # VID steps for the
margin.
00h = no margin,
01h = +1 VID step
02h = +2 VID steps
multiple VRs behavior on the
same SVID bus.
Rsum
Rsum
Rsum
Ro
Ro
Ro
Rntcs
DESCRIPTION
Rntc
n
. R
ntc
Rp
is a negative
sum
Cn
September 29, 2011
Ri
and R
Vcn
00h
00h
00h
VR1: 00h
VR2: 01h
ISUM+
DEFAULT
ISUM-
VALUE
o
FN6898.0
sum