st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 204

• Manufacturer Part Number: st7fmc2s7t6
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
• Manufacturer: STMicroelectronics

ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont’d)
10.6.10.5 Repetition Down-Counter
Both in center-aligned and edge-aligned modes,
the four Compare registers (one Compare 0 and
three for the U, V and W phases) are updated
when the PWM counter underflow or overflow and
the 8-bit Repetition down-counter has reached ze-
ro.
This means that data are transferred from the
preload compare registers to the compare regis-
ters every N cycles of the PWM Counter, where N
is the value of the 8-bit Repetition register in edge
-aligned mode. When using center-aligned mode,
the repetition down-counter is decremented every
time the PWM counter overflows or underflows. Al-
though this limits the maximum number of repeti-
tion to 128 PWM cycles, this makes it possible to
update the duty cycle twice per PWM period. As a
result, the effective PWM resolution in that case is
equal to the resolution we can get using edge-
Figure 122. Update rate examples depending on mode and MREP register settings
204/308
1
re-synchronization
MREP = 0
MREP = 1
MREP = 2
MREP = 3
MREP = 3
12-bit PWM
and
Counter
U
U Event: Preload registers transferred to active registers and PWM interrupt generated
U Event if transition from MREP = 0 to MREP = 1 occurs when 12-bit counter is equal
U
U
U
U
U
(by SW)
Center-aligned mode
to MCP0.
aligned mode, i.e. one T
ing compare registers only once per PWM period
in center-aligned mode, maximum resolution is
2xT
The repetition down counter is an auto-reload
type; the repetition rate will be maintained as de-
fined by the MREP register value (refer to
122).
10.6.10.6 PWM interrupt generation
A PWM interrupt is generated synchronously with
the “U” update event, which allows to refresh com-
pare values by software before the next update
event. As a result, the refresh rate for phases duty
cycles is directly linked to MREP register setting.
A signal reflecting the update events may be out-
put on a standard I/O port for debugging purposes.
Refer to
tails.
mtc
, due to the symmetry of the pattern.
section10.6.7.3 on page 171
(by SW)
Edge-aligned mode
mtc
period. When refresh-
for more de-
Figure