st10f273m STMicroelectronics, st10f273m Datasheet - Page 175

• Manufacturer Part Number: st10f273m
• Description: 16-bit Mcu With 512 Kbyte Flash Memory And 36 Kbyte Ram
• Manufacturer: STMicroelectronics

ST10F273M
Table 76.
t
t
t
t
t
t
t
t
t
310
311
312
313
314
315
316
317p
318p
Symbol
CC Write data valid after shift edge
CC Write data hold after shift edge
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
SR
SR
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
Figure 62. SSC master timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
2. The bit timing is repeated for all bits to be transmitted or received.
Slave mode
V
SSC slave mode timings
DD
SCLK
MTSR
MRST
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
= 5V ±10%, V
Parameter
(1)
(2)
t
SS
305
t
1st in bit
307
= 0V, T
1st out bit
t
300
t
308
A
Max. baudrate 6.6 Mbaud
= -40 to +125°C, C
t
305
t
301
(<SSCBR> = 0002h)
t
Min
150
304
63
63
62
87
@ f
–
0
–
–
2nd out bit
CPU
2nd In bit
t
302
= 40 MHz
t
303
Max
150
t
10
10
55
306
L
–
–
–
–
–
= 50pF
(1)
(2)
(<SSCBR> = 0001h - FFFFh)
t
t
4TCL + 12
6TCL + 12
310
310
8TCL
t
Min
/ 2 – 12
/ 2 – 12
305
Variable baudrate
–
–
–
0
Last in bit
t
Electrical characteristics
307
Last out bit
t
308
262144 TCL
2TCL + 30
Max
10
10
–
–
–
–
–
175/182
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns