st10f273m STMicroelectronics, st10f273m Datasheet - Page 165

• Manufacturer Part Number: st10f273m
• Description: 16-bit Mcu With 512 Kbyte Flash Memory And 36 Kbyte Ram
• Manufacturer: STMicroelectronics

ST10F273M
Table 72.
1. RW-delay and t
2.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
39
41
82
83
46
47
48
49
50
51
53
68
55
57
address changes before the end of RD have no impact on read cycles.
Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore
SR
CC
CC
CC
SR
SR
CC
CC
CC Data valid to WrCS
SR Data hold after RdCS
SR
SR
CC
CC Data hold after WrCS
Latched CS low to Valid
Data in
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS
(with RW-delay)
Address setup to RdCS,
WrCS
(no RW-delay)
RdCS to Valid Data in
(with RW-delay)
RdCS to Valid Data in
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Demultiplexed bus timings (continued)
A
Parameter
refer to the next following bus cycle
3
3
15.5 + t
14 + 2t
-8.5 + t
28 + t
10 + t
2 + 2t
2 + t
2 + t
Min
–
–
–
0
–
–
f
TCL = 12.5ns
CPU
F
F
A
C
C
A
F
C
= 40 MHz
16.5 + t
16.5 + t
16.5 + t
4 + t
4 + t
Max
–
–
–
–
–
–
–
–
–
C
C
F
+ 2t
C
F
A
TCL - 10.5 + 2t
2TCL - 11 + 2t
TCL - 10.5 + t
2TCL - 9.5 + t
3TCL - 9.5 + t
TCL - 10.5 + t
2TCL - 15 + t
-8.5 + t
Min
1/2 TCL = 1 to 40 MHz
–
–
–
0
–
–
Variable CPU Clock
F
C
F
C
C
F
A
A
Electrical characteristics
3TCL - 21 + t
2TCL - 8.5 + t
2TCL - 21 + t
3TCL - 21 + t
TCL - 8.5 + t
Max
–
–
–
–
–
–
–
–
–
C
+ 2t
F
C
C
F
A
165/182
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns