74LV74PW,118 NXP Semiconductors, 74LV74PW,118 Datasheet - Page 4

• Manufacturer Part Number: 74LV74PW,118
• Description: IC DUAL D FF POSEDG TRIG 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVr
• Type: D-Typer

Specifications of 74LV74PW,118

• Output Type: Differential
• Package / Case: 14-TSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 56MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LV
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 11 ns at 3.3 V
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1 V
• Delay Time - Propagation: -
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Frequency (max): 56MHz
• Operating Supply Voltage (min): 1V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74LV74PW-T; 74LV74PW-T; 935175140118

NXP Semiconductors
Table 2.
6. Functional description
Table 3.
[1]
Table 4.
[1]
74LV74_3
Product data sheet
Symbol (n = 1, 2)
nRD
nD
nCP
nSD
nQ
nQ
GND
V
Inputs
nSD
L
H
L
Inputs
nSD
H
H
CC
H = HIGH voltage level; L = LOW voltage level; X = don’t care
H = HIGH voltage level; L = LOW voltage level
Q
n+1
= LOW-to-HIGH transition
= state after the next LOW-to-HIGH CP transition
Pin description
Function table
Function table
5.2 Pin description
nRD
H
L
L
nRD
H
H
Pin
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
[1]
[1]
nCP
X
X
X
nCP
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
supply voltage
Rev. 03 — 28 September 2007
Dual D-type flip-flop with set and reset; positive edge-trigger
nD
X
X
X
nD
L
H
Outputs
nQ
H
L
H
Outputs
nQ
L
H
n+1
© NXP B.V. 2007. All rights reserved.
nQ
L
H
H
nQ
H
L
74LV74
n+1
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