74LV74PW,118 NXP Semiconductors, 74LV74PW,118 Datasheet - Page 12

• Manufacturer Part Number: 74LV74PW,118
• Description: IC DUAL D FF POSEDG TRIG 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVr
• Type: D-Typer

Specifications of 74LV74PW,118

• Output Type: Differential
• Package / Case: 14-TSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 56MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LV
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 11 ns at 3.3 V
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1 V
• Delay Time - Propagation: -
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Frequency (max): 56MHz
• Operating Supply Voltage (min): 1V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74LV74PW-T; 74LV74PW-T; 935175140118

NXP Semiconductors
12. Package outline
Fig 9. Package outline SOT27-1 (DIP14)
74LV74_3
Product data sheet
DIP14: plastic dual in-line package; 14 leads (300 mil)
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
inches
UNIT
mm
OUTLINE
VERSION
SOT27-1
max.
0.17
4.2
A
L
min.
0.51
0.02
A
Z
1
14
pin 1 index
1
050G04
IEC
max.
0.13
A
3.2
2
e
0.068
0.044
1.73
1.13
b
0.021
0.015
MO-001
0.53
0.38
JEDEC
b
D
1
Rev. 03 — 28 September 2007
REFERENCES
0
0.014
0.009
0.36
0.23
b
c
Dual D-type flip-flop with set and reset; positive edge-trigger
19.50
18.55
0.77
0.73
D
SC-501-14
(1)
JEITA
scale
5
b
8
7
1
6.48
6.20
0.26
0.24
E
(1)
A
w
1
M
2.54
0.1
e
A
E
10 mm
2
A
7.62
0.3
e
1
3.60
3.05
0.14
0.12
L
c
PROJECTION
EUROPEAN
8.25
7.80
0.32
0.31
M
(e )
M
M
E
H
1
E
10.0
0.39
0.33
M
8.3
H
© NXP B.V. 2007. All rights reserved.
ISSUE DATE
0.254
0.01
74LV74
99-12-27
03-02-13
w
SOT27-1
0.087
max.
2.2
Z
(1)
12 of 19