74LV74PW,118 NXP Semiconductors, 74LV74PW,118 Datasheet
74LV74PW,118
Specifications of 74LV74PW,118
74LV74PW-T
935175140118
Related parts for 74LV74PW,118
74LV74PW,118 Summary of contents
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Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 03 — 28 September 2007 1. General description The 74LV74 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC74 and 74HCT74. The device is ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV74N +125 C 74LV74D +125 C 74LV74DB +125 C 74LV74PW +125 C 74LV74PW +125 C 4. Functional diagram 1SD 1CP 1RD 1 2SD 2CP 2RD 13 Fig 1. Logic symbol 74LV74_3 Product data sheet Dual D-type flip-flop with set and reset; positive edge-trigger ...
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... NXP Semiconductors Fig 3. Logic diagram (one flip-flop) 5. Pinning information 5.1 Pinning 1 1RD 1CP 74 1SD GND 7 001aad106 Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 74LV74_3 Product data sheet Dual D-type flip-flop with set and reset; positive edge-trigger 2RD 12 2D ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol ( Pin nRD nCP 3, 11 nSD GND Functional description [1] Table 3. Function table Inputs nSD nRD [ HIGH voltage level LOW voltage level don’t care [1] Table 4. Function table Inputs nSD nRD [ HIGH voltage level LOW voltage level ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...
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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current CC I additional supply current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t propagation nCP to nQ, nQ; see pd delay nSD to nQ, nQ; nRD to nQ, nQ; see Figure pulse width clock HIGH or LOW; see W set or reset LOW ...
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... NXP Semiconductors Table 8. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t hold time nD to nCP; see maximum see Figure 6 max frequency power per flip-flop dissipation capacitance [1] Typical values are measured at T ...
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... NXP Semiconductors 11. Waveforms nD input nCP input nQ output nQ output The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 6. The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, ...
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... NXP Semiconductors nCP input nSD input nRD input nQ output nQ output Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 7. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths, and the nRD to nCP recovery time Table 9 ...
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... NXP Semiconductors Test data is given in Table 10. Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 8. Load circuit for switching times Table 10. ...
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... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. 1.73 mm 4.2 0.51 3.2 1.13 0.068 inches 0.17 0.02 0.13 0.044 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 11. Package outline SOT337-1 (SSOP14) ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0.30 3 0.2 0.00 0.18 2.9 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Document ID Release date 74LV74_3 20070928 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name when appropiate. • Section • Section • ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 Revision history ...